Decision feedback equalization employing a lookup table

• US 20030202617A1
• Filed: 04/24/2002
• Published: 10/30/2003
• Est. Priority Date: 04/24/2002
• Status: Active Grant

• Current Assignee: Beijing Xiaomi Mobile Software Co., Ltd. (Xiaomi Corp.)
• Original Assignee: Intel Corporation
• Inventors: Casper, Bryan K.
• Granted Patent: US 6,724,329 B2
• Time in Patent Office: Days
• US Class Current: 375/317
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence

Abstract

A decision feedback equalizer includes a lookup table device. The lookup table device may include a shift register and memory, or may include multiple shift registers and memories. Near-end crosstalk may be reduced using a lookup table device. Echo in a bi-directional port circuit may also be reduced using a lookup table device.

Claims

1. A circuit comprising:

a variable offset comparator having a signal input node, a digital control input, and a digital output node; and

a lookup table device coupled between the digital output node and the digital control input of the variable offset comparator.

2. The circuit of claim 1 wherein the variable offset comparator comprises:

first and second differential transistor pairs; and

first and second variable current generators coupled to the first and second differential transistor pairs, respectively, wherein the first and second variable current generators are coupled to be responsive to the digital control input.

3. The circuit of claim 1 wherein the variable offset comparator comprises:

a voltage-to-current converter coupled between the signal input node and a current summing node; and

a digital-to-analog converter having a current output, the digital-to-analog converter coupled between the digital control input and the current summing node.

4. The circuit of claim 1 wherein the lookup table device includes a shift register and a memory.

5. The circuit of claim 4 further comprising a lookup table programming control circuit to fill the memory with digital data.

6. The circuit of claim 1 wherein the lookup table device includes a finite impulse response filter including a group of taps implemented with a memory device.

7. The circuit of claim 6 wherein the finite impulse response filter further includes a plurality of groups of taps, each of the plurality of groups of taps having a shift register and a memory device.

8. The circuit of claim 1 further comprising:

a driver coupled to drive an output signal on the signal input node; and

an echo cancellation node coupled between the driver and the lookup table device to provide an indication of data driven by the driver to the lookup table device.

9. The circuit of claim 8 wherein the lookup table device includes:

a first shift register coupled to receive data from the digital output node;

a second shift register coupled to receive the indication of data driven by the driver; and

a memory device coupled to receive address bits from the first and second shift registers, and coupled to provide a digital control word to the digital control input.

10. The circuit of claim 1 further comprising:

a driver coupled to drive an output node other than the signal input node; and

a near-end crosstalk cancellation node coupled between the driver and the lookup table device to provide an indication of data driven by the driver to the lookup table device.

11. The circuit of claim 10 wherein the lookup table device includes:

a first shift register coupled to receive data from the digital output node;

a second shift register coupled to receive the indication of data driven by the driver; and

a memory device coupled to receive address bits from the first and second shift registers, and coupled to provide a digital control word to the digital control input.

12. An integrated circuit comprising:

an interface node electrically accessible from inside and outside the integrated circuit;

a receiver having an input node coupled to the interface node; and

a decision feedback equalizer that includes a lookup table device coupled to receive data output from the receiver;

wherein the receiver is configured to be responsive to a digital control word generated by the decision feedback equalizer.

13. The integrated circuit of claim 12 wherein the receiver comprises a variable offset comparator having a variable offset responsive to the digital control word.

14. The integrated circuit of claim 13 wherein the lookup table device comprises:

a shift register to receive data output from the receiver; and

a memory device coupled to receive an output from the shift register, and coupled to provide the digital control word.

15. The integrated circuit of claim 12 further comprising:

a driver having an output node coupled to the interface node; and

a signal path from the driver to the decision feedback equalizer to reduce the effects of echo contributed by the driver.

16. The integrated circuit of claim 15 further including a training data circuit coupled to an input to the driver to drive a training data sequence on the interface node.

17. The integrated circuit of claim 12 further including a lookup table programming control circuit to program data into the lookup table device.

18. The integrated circuit of claim 12 wherein the decision feedback equalizer comprises a finite impulse response filter including:

a first shift register having a first parallel output node;

a second shift register having a second parallel output node;

a first memory device responsive to the first parallel output node; and

a second memory device responsive to the second parallel output node.

19. An electronic system comprising:

a first integrated circuit including a driver having an input node, and including a training data circuit to conditionally drive the input node of the driver with training data;

a signal conductor coupled to an output node of the driver in the first integrated circuit; and

a second integrated circuit including a receiver coupled to the signal conductor, the receiver having a variable offset comparator and a decision feedback equalizer, the decision feedback equalizer including a lookup table to apply a digital offset control word to the variable offset comparator, and a circuit to fill the lookup table in response to the training data.

20. The electronic system of claim 19 wherein the decision feedback equalizer comprises a shift register coupled to receive data from an output node of the variable offset comparator, and wherein the lookup table is coupled between parallel output nodes of the shift register and a digital offset control input node of the variable offset comparator.

21. The electronic system of claim 19 wherein the second integrated circuit includes a driver having an output node coupled to the signal conductor.

22. The electronic system of claim 21 wherein the decision feedback equalizer is configured to be responsive to data values transmitted by the driver in the second integrated circuit to reduce the effects of echo caused by the driver in the second integrated circuit.

23. The electronic system of claim 22 wherein the decision feedback equalizer comprises:

a first shift register coupled to receive data from an output node of the variable offset comparator; and

a second shift register coupled to receive the data values transmitted by the driver in the second integrated circuit, wherein the lookup table is coupled between parallel output nodes of the first and second shift registers and a digital offset control input node of the variable offset comparator.

24. The electronic system of claim 19 further comprising:

a second signal conductor coupled between the first and second integrated circuits; and

a driver in the second integrated circuit having an output node coupled to the second signal conductor, wherein the decision feedback equalizer is configured to be responsive to data values transmitted by the driver in the second integrated circuit to reduce the effects of near-end crosstalk caused by the driver in the second integrated circuit.

25. The electronic system of claim 24 wherein the decision feedback equalizer comprises:

a first shift register coupled to receive data from an output node of the variable offset comparator; and

a second shift register coupled to receive the data values transmitted by the driver in the second integrated circuit, wherein the lookup table is coupled between parallel output nodes of the first and second shift registers and a digital offset control input node of the variable offset comparator.

26. The electronic system of claim 19 wherein the decision feedback equalizer comprises:

a first shift register having a first parallel output node and a serial output node;

a second shift register having a serial input node coupled to the serial output node of the first shift register, and having a second parallel output node;

a first lookup table coupled to the first parallel output node;

a second lookup table coupled to the second parallel output node; and

an adder circuit to sum digital outputs of the first and second lookup tables and apply a sum to the variable offset comparator.