High voltage power MOSFET having a voltage sustaining region that includes doped columns formed by trench etching and diffusion from regions of oppositely doped polysilicon

• US 20030203552A1
• Filed: 04/16/2003
• Published: 10/30/2003
• Est. Priority Date: 12/31/2001
• Status: Active Grant

• Current Assignee: Richard A. Blanchard
• Original Assignee: Richard A. Blanchard
• Inventors: Blanchard, Richard A.
• Granted Patent: US 6,794,251 B2
• Time in Patent Office: Days
• US Class Current: 438/200
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

Claims

1. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first or second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. depositing in said trench a first layer of material having a second dopant of the second conductivity type;

4. diffusing said second dopant to form a doped epitaxial region adjacent to said trench and in said epitaxial layer;

5. depositing in said trench a second layer of material having a first dopant of the first conductivity type;

6. interdiffusing the first and second dopants respectively located in the second and first layers of material to achieve electrical compensation in the first and second layers of material;

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.

2. The method of claim 1 wherein said electrical compensation is sufficient to substantially achieve charge neutrality in the first and second layers of material.

3. The method of claim 1 wherein the second layer substantially fills the trench.

4. The method of claim 1 wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.

5. The method of claim 1 wherein said second dopant is boron.

6. The method of claim 1 wherein said first dopant includes phosphorus.

7. The method of claim 1 wherein said first dopant includes arsenic.

8. The method of claim 1 wherein said first dopant includes phosphorus and arsenic.

9. The method of claim 4 wherein said body regions include deep body regions.

10. The method of claim 1, wherein said trench is formed by providing a masking layer defining at least one trench, and etching the trench defined by the masking layer.

11. The method of claim 4, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

12. The method of claim 1 wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a diode and a bipolar transistor.

13. The method of claim 1 wherein said first and second layers of material are layers of polysilicon.

14. The method of claim 2 wherein said first and second layers of material are layers of polysilicon.

15. The method of claim 3 wherein said first and second layers of material are layers of polysilicon.

16. The method of claim 4 wherein said first and second layers of material are layers of polysilicon.

17. The method of claim 1 further comprising the step of diffusing a portion of the first dopant into said doped epitaxial region to adjust the electrical charge of said doped epitaxial region.

18. A power semiconductor device made in accordance with the method of claim 1.

19. A power semiconductor device made in accordance with the method of claim 16.

20. A power semiconductor device made in accordance with the method of claim 12.

21. A power semiconductor device comprising:

a substrate of a first or second conductivity type;

a voltage sustaining region disposed on said substrate, said voltage sustaining region including;

an epitaxial layer having a first conductivity type;

at least one trench located in said epitaxial layer;

a first layer of material located in the trench;

a second layer of material located over the first layer of polysilicon;

at least one doped column located adjacent to the trench and in the epitaxial layer, said at least one doped column having a dopant of the second conductivity type, said at least one doped column being formed by diffusion of the second dopant from the first layer of material into the epitaxial layer;

at least one region of said second conductivity disposed over said voltage sustaining region to define a junction therebetween.

22. The device of claim 21 wherein said first and second layers of material are high resistivity layers of material.

23. The device of claim 21 wherein said first and second layers of material are substantially electrically neutral.

24. The device of claim 21 wherein said at least one region further includes:

a gate dielectric and a gate conductor disposed above said gate dielectric;

first and second body regions located in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type; and

first and second source regions of the first conductivity type located in the first and second body regions, respectively.

25. The device of claim 24 wherein said body regions include deep body regions.

26. The device of claim 21 wherein the second layer substantially fills the trench.

27. The device of claim 21 wherein said dopant is boron.

28. The device of claim 21 further comprising a first dopant diffused from the second layer to the first layer.

29. The device of claim 23 further comprising another dopant diffused from the second layer to the first layer to achieve the electrical neutrality in the first and second layers of material.

30. The device of claim 29 wherein said another dopant includes arsenic.

31. The device of claim 29 wherein said another dopant includes phosphorus.

32. The device of claim 29 wherein said another dopant includes phosphorus and arsenic.

33. The device of claim 21 wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a diode and a bipolar transistor.

34. The device of claim 21 wherein said first and second layers of material are layers of polysilicon.

35. The device of claim 22 wherein said first and second layers of material are layers of polysilicon.

36. The device of claim 23 wherein said first and second layers of material are layers of polysilicon.

37. The device of claim 24 wherein said first and second layers of material are layers of polysilicon.

38. The device of claim 29 wherein said first and second layers of material are layers of polysilicon.

39. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first or second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. providing in said trench a first layer of material having a second dopant of the second conductivity type;

4. diffusing said second dopant to form a doped epitaxial region adjacent to said trench and in said epitaxial layer;

5. providing in said trench a second layer of material having a first dopant of the first conductivity type;

6. interdiffusing the first and second dopants respectively located in the second and first layers of material to achieve electrical compensation in the first and second layers of material;

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.

40. The method of claim 39 wherein said electrical compensation is sufficient to substantially achieve charge neutrality in the first and second layers of material.

41. The method of claim 39 wherein the second layer substantially fills the trench.

42. The method of claim 39 wherein step (C) further includes the steps of:

forming a gate conductor above a gate dielectric region;

forming first and second body regions in the epitaxial layer to define a drift region therebetween, said body regions having a second conductivity type;

forming first and second source regions of the first conductivity type in the first and second body regions, respectively.

43. The method of claim 39 wherein said second dopant is boron.

44. The method of claim 39 wherein said first dopant includes phosphorus.

45. The method of claim 39 wherein said first dopant includes arsenic.

46. The method of claim 39 wherein said first dopant includes phosphorus and arsenic.

47. The method of claim 42 wherein said body regions include deep body regions.

48. The method of claim 39, wherein said trench is formed by providing a masking layer defining at least one trench, and etching the trench defined by the masking layer.

49. The method of claim 42, wherein said body region is formed by implanting and diffusing a dopant into the substrate.

50. The method of claim 39 wherein said power semiconductor device is selected from the group consisting of a vertical DMOS, V-groove DMOS, and a trench DMOS MOSFET, an IGBT, a diode and a bipolar transistor.

51. The method of claim 39 wherein the step of providing a first layer of material includes the steps of depositing a first layer of material followed by doping the first layer of material with the second dopant using gas phase doping.

52. The method of claim 51 wherein the step of providing a second layer of material includes the steps of depositing a second layer of material followed by doping the second layer of material with the first dopant using gas phase doping.

53. The method of claim 52 further comprising the step of filling the trench with a dielectric material.

54. The method of claim 52 further comprising the step of filling the trench with undoped polysilicon. 55. The method of claim 39 wherein said first and second layers of material are layers of polysilicon.

55. The method of claim 51 wherein said first and second layers of material are layers of polysilicon.

56. The method of claim 52 wherein said first and second layers of material are layers of polysilicon.

57. The method of claim 53 wherein said first and second layers of material are layers of polysilicon.

58. The method of claim 39 further comprising the step of diffusing a portion of the first dopant into said doped epitaxial region to adjust the electrical charge of said doped epitaxial region.

59. A method of forming a power semiconductor device comprising the steps of:

A. providing a substrate of a first or second conductivity type;

B. forming a voltage sustaining region on said substrate by;

1. depositing an epitaxial layer on the substrate, said epitaxial layer having a first conductivity type;

2. forming at least one trench in said epitaxial layer;

3. providing in said trench a first layer of material having a second dopant of the second conductivity type;

4. diffusing said second dopant to form a doped epitaxial region adjacent to said trench and in said epitaxial layer;

5. diffusing a first dopant of the first conductivity type into the first layer of material to achieve electrical compensation in the first layer of material;

C. forming over said voltage sustaining region at least one region of said second conductivity type to define a junction therebetween.