CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof

• US 20030203560A1
• Filed: 04/23/2003
• Published: 10/30/2003
• Est. Priority Date: 04/25/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Hee-Sung, Oh, Chang-Bong, Kim, Young-Wug, Ryu, Hyuk-Ju
• Granted Patent: US 6,855,641 B2
• Time in Patent Office: Days
• US Class Current: 438/218
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors

Abstract

In a CMOS semiconductor device using a silicon germanium gate and a method of fabricating the same, a gate insulating layer, a conductive electrode layer that is a seed layer, a silicon germanium electrode layer, and an amorphous conductive electrode layer are sequentially formed on a semiconductor substrate. A photolithographic process is then carried out to remove the silicon germanium electrode layer in the NMOS region, so that the silicon germanium layer is formed only in the PMOS region and is not formed in the NMOS region.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming a gate oxide layer on a semiconductor substrate, a device isolation region being formed on the substrate to define an NMOS region and a PMOS region;

sequentially forming a silicon germanium layer and an amorphous conductive layer on the gate oxide layer;

removing the amorphous conductive layer and the silicon germanium layer in the NMOS region;

forming a polysilicon layer on the semiconductor substrate in the NMOS region; and

until the gate insulating layer is exposed, patterning the stacked conductive layers to form gate electrodes the NMOS and PMOS regions respectively.

2. The method as recited in claim 1, wherein the removing the amorphous conductive layer and the silicon germanium layer in the NMOS region comprises:

forming a mask pattern on the amorphous conductive layer in the PMOS region;

performing a dry etch using the mask pattern; and

performing a wet etch after removing the mask pattern.

3. The method as recited in claim 2, wherein the dry etch is performed to completely remove the amorphous conductive layer and to partially remove the underlying silicon germanium layer.

4. The method as recited in claim 3, wherein the wet etch is performed to selectively remove a residue of the amorphous conductive layer exposed by the dry etch.

5. The method as recited in claim 2, wherein the dry etch uses a gas containing carbon atoms and fluorine atoms and the wet etch uses a mixed etchant of HNO₃ and H₂O₂ solutions.

6. The method as recited in claim 1, wherein the amorphous conductive layer is made of amorphous silicon.

7. The method as recited in claim 1, further comprising forming a silicon seeding layer for the silicon germanium layer after forming the gate oxide layer and before forming the silicon germanium layer.

8. The method as recited in claim 7, wherein the removing the amorphous conductive layer and the silicon germanium layer in the NMOS region comprises:

forming a mask pattern on the amorphous conductive layer in the PMOS region;

performing a dry etch using the mask pattern;

removing the mask pattern; and

performing a wet etch,

wherein the dry etch is performed to completely etch the amorphous conductive layer and to partially etch the underlying silicon germanium layer and the wet etch is performed to selectively etch a remaining portion of the silicon germanium layer down to a top surface of the silicon layer for seeding.

9. The method as recited in claim 7, wherein the silicon seeding layer comprises polysilicon.

10. The method as recited in claim 9, further comprising implanting impurities into the silicon seeding layer after forming the mask pattern or performing the dry etch before removing the mask pattern.

11. The method as recited in claim 8, wherein the dry etch uses a gas containing carbon atoms and fluorine atoms and the wet etch uses a mixed etchant of HNO₃ and H₂O₂ solutions.

12. The method as recited in claim 7, further comprising annealing the semiconductor substrate at any time after forming the silicon germanium layer.

13. A method of fabricating a semiconductor device, comprising:

forming a gate oxide layer on a semiconductor substrate, a device isolation region being formed on the substrate to define an NMOS region and a PMOS region;

forming a lower polysilicon electrode seeding layer on the gate oxide layer;

forming a silicon germanium electrode layer on the lower polysilicon electrode seeding layer;

forming an amorphous electrode layer on the silicon germanium electrode layer;

forming a mask pattern on the amorphous electrode layer in the PMOS region so as to expose the NMOS region;

dry-etching the amorphous electrode layer and a portion of the underlying silicon germanium electrode layer in the NMOS region exposed by the mask pattern;

removing the mask pattern;

selectively wet-etching a residue of the silicon germanium electrode layer exposed by the dry etch down to a top surface of the lower polysilicon electrode seeding layer in the NMOS region;

forming upper polysilicon electrode layers on the lower polysilicon electrode seeding layer in the NMOS region and the silicon germanium electrode layer in the PMOS region, respectively; and

patterning the stacked electrode layers to form gate electrodes in the NMOS and PMOS regions, respectively.

14. The method as recited in claim 13, further comprising performing an annealing process so as to diffuse germanium of the silicon germanium electrode layer to the lower polysilicon electrode seeding layer at any time subsequent to forming the silicon germanium electrode layer.

15. The method as recited in claim 14, wherein the amorphous silicon layer formed on the silicon germanium electrode layer serves to prevent the germanium from diffusing to the upper polysilicon electrode layer in the annealing process.

16. The method as recited in claim 15, wherein the amorphous electrode layer comprises amorphous silicon.

17. The method as recited in claim 13, wherein the dry etch uses gas containing carbon atoms and fluorine atoms.

18. The method as recited in claim 13, wherein the wet etch uses a mixed etchant of HNO₃ of 1.2 volume percent and H₂O₂ of 4.8 volume percent.

19. The method as recited in claim 13, after forming gate electrodes on the NMOS and PMOS regions respectively, further comprising:

forming an insulating layer sidewall spacer on both sidewalls of the respective gate electrode;

using the sidewall spacer and the gate electrode as an ion implanting mask, forming source/drain regions in the semiconductor substrate adjacent side portions of the gate electrode; and

forming a refractory metal layer in the source/drain regions.

20. The method as recited in claim 19, further comprising performing an annealing process so as to diffuse the germanium of the silicon germanium electrode layer to the lower polysilicon electrode seeding layer at any time subsequent to forming the silicon germanium electrode layer.

21. The method as recited in claim 20, further comprising performing an annealing process after forming the refractory metal layer.

22. A semiconductor device having an NMOS transistor and a PMOS transistor defined in respective NMOS and PMOS regions respectively of a semiconductor substrate, each transistor having a gate insulating layer between a gate electrode and the semiconductor substrate;

wherein the gate electrode of the NMOS transistor consists of a lower polysilicon layer and an upper polysilicon layer which are sequentially stacked on the gate insulating layer;

wherein the gate electrode of the PMOS transistor consists of a lower polysilicon layer, a silicon germanium layer, a diffusion barrier amorphous silicon layer, and an upper polysilicon layer which are sequentially stacked on the gate insulating layer; and

wherein each of the transistors includes a source/drain regions formed in the semiconductor substrate adjacent side portions of the respective gate electrodes.

23. The semiconductor device as recited in claim 22, wherein the diffusion barrier amorphous silicon layer has a thickness ranging between 10 angstroms and 500 angstroms.

24. The semiconductor device as recited in claim 22, further comprising silicide layers which are formed on the upper polysilicon layers of the PMOS and NMOS transistors respectively.

25. The semiconductor device as recited in claim 22, further comprising insulating layer sidewall spacers which are formed on sidewalls of the gate electrodes of the NMOS and PMOS transistors respectively,

wherein the PMOS sidewall spacer is larger in thickness than the NMOS sidewall spacer, and wherein each spacer overlaps at least a portion of the underlying source/drain regions.