Method of manufacturing a transistor

• US 20030203576A1
• Filed: 03/31/2003
• Published: 10/30/2003
• Est. Priority Date: 03/01/2000
• Status: Active Grant

• Current Assignee: Shindengen Electric Manufacturing Company Limited
• Original Assignee: Shindengen Electric Manufacturing Company Limited
• Inventors: Takemori, Toshiyuki, Kunori, Shinji, Kitada, Mizue
• Granted Patent: US 6,706,615 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.

Claims

1. A transistor comprising:

a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type disposed on the semiconductor layer and an opposite conductive region of a second conductivity type disposed on the drain layer;

polysilicon containing impurities of the second conductivity type disposed in part of the drain layer;

a gate trench disposed from a surface of the opposite conductive region to the polysilicon;

a source region of the first conductivity type formed on the surface of the opposite conductive region at a position adjacent to the gate trench;

a gate insulating film positioned on the inner surface of the gate trench and disposed over the drain layer, the opposite conductive region and the source region; and

a gate electrode film disposed in the gate trench in tight contact with the gate insulating film and insulated from the polysilicon.

2. The transistor according to claim 1, wherein the polysilicon and the gate electrode film are insulated from each other by the gate insulating film.

3. The transistor according to claim 1, further comprising an insulating film which is disposed between the polysilicon and the drain layer and insulates the polysilicon from the drain layer.

4. The transistor according to claim 1, wherein the semiconductor layer is of the first conductivity type.

5. The transistor according to claim 1, wherein the semiconductor layer is of the second conductivity type.

6. A transistor comprising:

a semiconductor substrate having a semiconductor layer, a drain layer of a first conductivity type disposed on the semiconductor layer and an opposite conductive region of a second conductivity type disposed on the drain layer;

a semiconductor material disposed in part of the drain layer and constituted so that a depletion layer can be formed therein;

a gate trench disposed from a surface of the opposite conductive region to the semiconductor material;

a source region of the first conductivity type formed on the surface of the opposite conductive region at a position adjacent to the gate trench;

a gate insulating film positioned on the inner surface of the gate trench and disposed over the drain layer, the opposite conductive region and the source region; and

a gate electrode film disposed in the gate trench in tight contact with the gate insulating film and insulated from the semiconductor material, wherein the semiconductor material is filled at the bottom of a deep trench disposed from the surface of the opposite conductive region to the inside of the drain layer; and

the gate trench is formed by the surface of the semiconductor material and the inner peripheral surface of the deep trench.

7. The transistor according to claim 6, wherein the semiconductor material and the gate electrode film are insulated from each other by the gate insulating film.

8. The transistor according to claim 6, further comprising an insulating film provided on the inner wall surface and the bottom surface of the deep trench;

and

wherein the semiconductor material is filled at the bottom of the deep trench so as to come into tight contact with the insulating film.

9. The transistor according to claim 6, wherein the semiconductor material is formed by epitaxial growth.

10. The transistor according to claim 6, wherein the semiconductor layer is of the first conductivity type.

11. The transistor according to claim 6, wherein the semiconductor layer is of the second conductivity type.

12. A method of manufacturing a transistor, comprising the steps of:

forming a deep trench in a semiconductor substrate having a drain layer of a first conductivity type and an opposite conductive region of a second conductivity type disposed on the drain layer from a surface of the opposite conductive region to the drain layer;

filling a semiconductor material in the deep trench from the bottom surface of the deep trench to a depth not reaching the opposite conductive region to be constituted so that a depletion layer can be formed therein;

forming a gate insulating film from the surface of the semiconductor material over the inner surface of the gate trench constituted by the surface of the semiconductor material and the deep trench;

forming a gate electrode film in which impurities of the first conductivity type are diffused in the gate trench so as to come into tight contact with the gate insulating film, and

forming a source region of the first conductivity type in the semiconductor substrate surface surrounding the gate trench.

13. The method of manufacturing a transistor according to claim 12, wherein

the step of filling the semiconductor material in the deep trench comprises the steps of:

forming an insulating film from the bottom surface of the deep trench to a depth not reaching the opposite conductive region; and

forming the semiconductor material on the insulating film surface and filling the deep trench with the semiconductor material to the upper end of the insulating film.

14. The method of manufacturing a transistor according to claim 12, wherein the semiconductor material is formed by epitaxial growth and is composed of silicon containing impurities of the second conductivity type.

15. The method of manufacturing a transistor according to claim 12, wherein the semiconductor material is composed of polysilicon containing impurities of the second conductivity type.