Communications system using rings architecture

• US 20030204636A1
• Filed: 07/02/2002
• Published: 10/30/2003
• Est. Priority Date: 07/02/2001
• Status: Abandoned Application

• Current Assignee: GlobespanVirata, Inc. (Synaptics Incorporated)
• Original Assignee: GlobespanVirata, Inc. (Synaptics Incorporated)
• Inventors: Greenblat, Ilia, Weitz, Elizer, Rafaeli, Moshe
• Application Number:
  US10/064,341
• Publication Number:
  US 20030204636A1
• Time in Patent Office: Days
• US Class Current: 709/251
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/422 Synchronisation for ring networks Time Division Multiplex ring networks, e.g. SDH/SONET H04J3/085
• CPC Class Codes: H04L 12/427 with decentralised control
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 12/437 Ring fault isolation or reconfiguration for SDH/SONET ring networks H04J3/085
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 12/4637 Interconnected ring systems
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5612 Ring
• CPC Class Codes: H04L 2012/5618 Bridges, gateways [GW] or interworking units [IWU]
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5656 using the AAL2
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 45/04 Interdomain routing, e.g. hierarchical routing
• CPC Class Codes: H04L 45/18 Loop-free operations
• CPC Class Codes: H04L 45/22 Alternate routing
• CPC Class Codes: H04L 45/302 Route determination based on requested QoS
• CPC Class Codes: H04L 45/306 : Route determination based on the nature of the carried application
• CPC Class Codes: H04L 45/50 : using label swapping, e.g. multi-protocol label switch [MPLS]
• CPC Class Codes: H04L 49/102 : using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/1553 : Interconnection of ATM switching modules, e.g. ATM switching fabrics
• CPC Class Codes: H04L 49/25 : Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/30 : Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 : Pipelined operation
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/40 : Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 69/12 : Protocol engines
• CPC Class Codes: H04W 28/06 : Optimizing the usage of the radio link, e.g. header compression, information sizing , discarding information system modifying transmission characteristic according to link quality by modifying frame length H04L1/0007; dynamic adaptation of the packet size for flow control or congestion control H04L47/365
• CPC Class Codes: H04W 40/00 : Communication routing or communication path finding
• CPC Class Codes: H04W 80/00 : Wireless network protocols or protocol adaptations to wireless operation
• CPC Class Codes: H04W 84/00 : Network topologies
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are provided for implementing: a rings architecture for communications and data handling systems; an enumeration process for automatically configuring the ring topology; automatic routing of messages through bridges; extending a ring topology to external devices; write-ahead functionality to promote efficiency; wait-till-reset operation resumption; in-vivo scan through rings topology; staggered clocking arrangement; and stray message detection and eradication. Other inventive elements conveyed include: an architectural overview of a packet processor; a programming model for a packet processor; an instruction pipeline for a packet processor; and use of a packet processor as a module on a rings-based architecture. Additional inventive elements conveyed include: an architectural overview of a communications processor; a data path protocol support model for a communications processor; an exemplary network processor employed as the core packet processor for the communications processor; an exemplary rings-based SOC switch fabric architecture; and a variety of quality of support features.

Claims

1. A communications processor implemented as on at least one ring network, comprising:

a plurality of processors comprising ring members on the at least one ring network;

a plurality of DMA controllers on the at least one ring network, the DMA controllers controlling servicing of DMA requests by the plurality of processors;

a plurality of DMA agents coupled to the plurality of processors, each DMA agent being part of a ring member including a processor;

each DMA agent adapted to issue an indicator to a request counter coupled to the DMA agent for each DMA request issued by the DMA agent to a DMA controller;

thereby allowing each DMA agent to maintain a count of the outstanding DMA requests that have been issued on behalf of the processor associated with the DMA agent.

2. The system of claim 1, wherein the request counter maintains a separate count for each task being executed by the processor.

3. The system of claim 1, wherein upon satisfaction of the DMA request by a target DMA controller, the target DMA controller issues a response that causes the request counter to decrement the count by one.

4. The system of claim 3, wherein the DMA requests issued by the DMA agent to the DMA controller and the response issued by the target DMA controller are transmitted as messages on the at least one ring network.

5. The system of claim 3, wherein upon the counter returning to zero the processor is enabled to switch to other tasks because all DMA requests for a given task have been satisfied.

6. The system of claim 5, whereupon a new DMA request for a different task is deferred until the counter has returned to zero for the given task.

7. The system of claim 2, wherein the request counter is contained in a doorbell register supporting up to 64 tasks.

8. A method of controlling access to DMA controllers in a multi-tasking communications processor implemented as on at least one ring network, comprising:

issuing DMA requests to a target DMA controller;

maintaining a count of DMA requests on a per-task basis;

issuing an acknowledgement that a DMA request has been satisfied by the target DMA controller;

reducing the count based on the acknowledgement; and

enabling a processor responsible for issuing the DMA requests to perform new activity when the count has returned to zero.

9. The method of claim 8, wherein the DMA requests are issued as messages on the at least one ring network.

10. The method of claim 8, wherein the acknowledgement is issued as a message on the at least one ring network.