Data transfer control device, electronic instrument, and data transfer control method

• US 20030204660A1
• Filed: 03/19/2003
• Published: 10/30/2003
• Est. Priority Date: 03/20/2002
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Sato, Daisuke, Saito, Nobuyuki, Oka, Yoshimi
• Granted Patent: US 7,054,959 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

A processing section reserves a number of transfers for an isochronous packet which includes isochronous data in an transfer number reservation register TNREG. A DMAC1 reads that isochronous packet from SRAM, and the thus-read isochronous packet is transferred automatically to a BUS1 (IEEE 1394 or USB) side at each isochronous transfer cycle until the number of transfers reserved in TNREG reaches zero. An SRAM header area is divided into page K and page L areas, and registers TNREGK and TNREGL are provided for reserving a number of transfers for each of the page K and L areas. During a special reproduction, a data pointer is used to select a TS packet which includes an I picture, for automatic transfer to the BUS1 side.

Claims

1. A data transfer control device for data transfer through a bus, comprising:

a transfer number reservation register which is used by a processing section to reserve a number of transfers for an isochronous packet which includes isochronous data; and

a first memory access control circuit which reads an isochronous packet from a first memory and automatically transfers the thus-read isochronous packet to a first bus side in each isochronous transfer cycle, until a number of transfers which is reserved in the transfer number reservation register reaches zero.

2. The data transfer control device as defined in claim 1, wherein:

when a number of transfers reserved in the transfer number reservation register has reached zero, the first memory access control circuit halts the automatic transfer at the next isochronous transfer cycle and outputs an interrupt to the processing section.

3. The data transfer control device as defined in claim 1, wherein:

a storage area of the first memory includes a header area and a data area;

the header area includes Kth and Lth page areas;

the transfer number reservation register includes transfer number reservation registers for the Kth and Lth pages, for reserving a number of transfers for the Kth and Lth page areas; and

while the processing section is preparing an isochronous header to be written to the Kth page area, the first memory access control circuit reads an isochronous header written to the Lth page area and isochronous data written to the data area, and automatically transfers an isochronous packet configured of the thus-read isochronous header and isochronous data, to the first bus side in each isochronous transfer cycle, until a number of transfers which is reserved in the transfer number reservation register for the Lth page reaches zero.

4. The data transfer control device as defined in claim 2, wherein:

a storage area of the first memory includes a header area and a data area;

the header area includes Kth and Lth page areas;

the transfer number reservation register includes transfer number reservation registers for the Kth and Lth pages, for reserving a number of transfers for the Kth and Lth page areas; and

while the processing section is preparing an isochronous header to be written to the Kth page area, the first memory access control circuit reads an isochronous header written to the Lth page area and isochronous data written to the data area, and automatically transfers an isochronous packet configured of the thus-read isochronous header and isochronous data, to the first bus side in each isochronous transfer cycle, until a number of transfers which is reserved in the transfer number reservation register for the Lth page reaches zero.

5. The data transfer control device as defined in claim 1, wherein:

a storage area of the first memory includes a header area and a data area;

a data pointer which indicates an address in the data area for isochronous data to be combined with an isochronous header is written to the header area; and

,

the first memory access control circuit assembles an isochronous packet configured of the isochronous header and isochronous data by using the data pointer, for automatic transfer to the first bus side.

6. The data transfer control device as defined in claim 5, wherein:

when isochronous data which is written to the data area includes a plurality of second-layer packets located lower than isochronous packets, the first memory access control circuit uses the data pointer to sort a second-layer packet which is to be transferred to the first bus side from a second-layer packet which is not to be transferred to the first bus side.

7. The data transfer control device as defined in claim 6, wherein:

during special reproduction of a storage medium, the first memory access control circuit uses the data pointer to select a second-layer packet including an I picture and automatically transfer the thus-selected second-layer packet to the first bus side.

8. The data transfer control device as defined in claim 1, further comprising:

a third memory access control circuit which writes isochronous data transferred from a second bus side connected to a storage medium, into a second memory having a larger capacity than the first memory; and

a second memory access control circuit which reads isochronous data written to the second memory and writes the thus-read isochronous data into the first memory,

wherein the first memory access control circuit reads from the first memory an isochronous packet having isochronous data written to the first memory, and automatically transfers the thus-read isochronous packet to the first bus side in each isochronous transfer cycle, until a number of transfers reserved in the transfer number reservation register reaches zero.

9. The data transfer control device as defined in claim 8, wherein:

the second memory is a synchronized type of memory which is capable of inputting and outputting data having sequential addresses in synchronization with a clock.

10. The data transfer control device as defined in claim 8, wherein:

the first memory is internal memory provided within the data transfer control device, and the second memory is external memory provided outside the data transfer control device.

11. The data transfer control device as defined in claim 9, wherein:

the first memory is internal memory provided within the data transfer control device, and the second memory is external memory provided outside the data transfer control device.

12. An electronic instrument comprising:

the data transfer control device as defined in claim 1;

and

a storage medium connected to the second bus of the data transfer control device, for storing data transferred through the second bus.

13. An electronic instrument comprising:

the data transfer control device as defined in claim 2;

and

a storage medium connected to the second bus of the data transfer control device, for storing data transferred through the second bus.

14. An electronic instrument comprising:

the data transfer control device as defined in claim 3;

and

a storage medium connected to the second bus of the data transfer control device, for storing data transferred through the second bus.

15. An electronic instrument comprising:

the data transfer control device as defined in claim 5;

and

a storage medium connected to the second bus of the data transfer control device, for storing data transferred through the second bus.

16. An electronic instrument comprising;

the data transfer control device as defined in claim 8;

and

a storage medium connected to the second bus of the data transfer control device, for storing data transferred through the second bus.

17. A data transfer control method for data transfer through a bus, the method comprising:

reserving a number of transfers for an isochronous packet which includes isochronous data, in a transfer number reservation register; and

reading an isochronous packet from a first memory, and automatically transferring the thus-read isochronous packet to a first bus side in each isochronous transfer cycle, until a number of transfers reserved in the transfer number reservation register reaches zero.

18. The data transfer control method as defined in claim 17, wherein:

when a number of transfers reserved in the transfer number reservation register has reached 2ero, the automatic transfer is halted at the next isochronous transfer cycle and an interrupt is outputted to the processing section.

19. The data transfer control method as defined in claim 17, wherein:

a storage area of the first memory includes a header area and a data area;

the header area includes Kth and Lth page areas;

the transfer number reservation register includes transfer number reservation registers for the Kth and Lth pages, for reserving a number of transfers for the Kth and Lth page areas; and

while the processing section is preparing an isochronous header to be written to the Kth page area, an isochronous header which is written to the Lth page area and isochronous data which is written to a data area are read, and an isochronous packet configured of the thus-read isochronous header and isochronous data is automatically transferred to the first bus side in each isochronous transfer cycle, until a number of transfers which is reserved in the transfer number reservation register for the Lth page reaches zero.

20. The data transfer control method as defined in claim 17, wherein:

a storage area of the first memory includes a header area and a data area;

a data pointer which indicates an address in the data area for isochronous data to be combined with an isochronous header is written to the header area; and

an isochronous packet configured of the isochronous header and isochronous data is assembled by using the data pointer, for automatic transfer to the first bus side.