Method and apparatus for selectively transmitting command signal and address signal

• US 20030204688A1
• Filed: 04/25/2003
• Published: 10/30/2003
• Est. Priority Date: 04/27/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dong-Yang
• Granted Patent: US 7,366,827 B2
• Time in Patent Office: Days
• US Class Current: 711/158
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for transmitting a command signal and an address signal to a rank which is to be accessed includes receiving and buffering the command signal and the address signal, and transmitting the buffered command signal and address signal to the rank, in response to a clock signal and a select signal for accessing rank. Transmitting the buffered command signal and address signal to the rank includes latching the buffered command signal and address signal, in response to the select signal, and transmitting the latched command signal and address signal to the rank, in response to the clock signal. The method and an associated apparatus can selectively transmit a command signal and an address signal to a rank or plurality of memory devices in a memory module, thereby reducing the amount of current consumed by memory modules that are not to be accessed.

Claims

1. A method for transmitting a command signal and an address signal to a rank which is to be accessed, the method comprising:

receiving and buffering the command signal and the address signal; and

transmitting the buffered command signal and address signal to the rank in response to a clock signal and a select signal for accessing the rank.

2. The method of claim 1, wherein the transmitting the buffered command signal and address signal to the rank includes:

latching the buffered command signal and address signal in response to the select signal; and

transmitting the latched command signal and address signal to the rank in response to the clock signal.

3. A method for transmitting a command signal and an address signal to a plurality of memory devices which are to be accessed, the method comprising:

receiving and buffering the command signal and the address signal; and

transmitting the buffered command signal and address signal to the memory devices in response to a clock signal and a select signal for accessing the memory devices.

4. The method of claim 3, wherein the transmitting the buffered command signal and address signal to the memory devices includes:

latching the buffered command signal and address signal in response to the select signal; and

transmitting the latched command signal and address signal to the memory devices in response to the clock signal.

5. A register mounted on a memory module, for transmitting a command signal and an address signal to a rank mounted on the memory module which is to be accessed, the register comprising:

a buffer adapted to receive and buffer the command signal and the address signal; and

a latch adapted to transmit the buffered command signal and address signal to the rank, in response to a select signal for accessing the rank and a clock signal.

6. The register of claim 5, wherein the latch includes:

a first latch adapted to latch the buffered command signal and address signal in response to the select signal; and

a second latch adapted to transmit the latched command signal and address signal to the rank in response to the clock signal.

7. A register for transmitting a command signal and an address signal to a plurality of memory devices which are to be accessed, the register comprising:

a buffer adapted to receive and buffer the command signal and the address; and

a latch adapted to transmit the buffered command signal and address signal to the memory devices in response to a clock signal and a select signal for selecting the memory devices.

8. The register of claim 7, wherein the latch includes:

a first latch adapted to latch the buffered command signal and address signal in response to the select signal; and

a second latch adapted to transmit the latched command signal and address signal to the memory devices in response to the clock signal.

9. A memory module comprising:

a plurality of memory devices; and

a register adapted to receive and buffer a command signal and an address signal and adapted to transmit the buffered command signal and address signal to the memory devices which are to be accessed.

10. The memory module of claim 9, wherein the memory module is a dual inline memory module (DIMM).

11. The memory module of claim 9, wherein the register includes:

a buffer adapted to receive and buffer the command signal and the address signal;

a first latch, connected to the buffer, adapted to latch the buffered command signal and address signal in response to a select signal for accessing the memory devices; and

a second latch adapted to transmit an output signal of the first latch to the first memory device in response to a clock signal.

12. A system comprising:

a memory controller adapted to output an address signal, a command signal and a select signal;

a plurality of memory modules; and

a bus adapted to transmit the address signal, the command signal and the select signal to each memory module,

wherein each of the memory modules includes;

a plurality of memory devices; and

a register adapted to receive and buffer the command signal and the address signal and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the select signal for accessing the memory devices.

13. The system of claim 12, wherein the register includes:

a buffer adapted to receive and buffering the command signal;

a first latch connected to the buffer adapted to latch and output signal of the buffer in response to the select signal; and

a second latch adapted to transmit an output signal of the first latch to the first memory device in response to a clock signal.

14. The system of claim 14, wherein each of the memory modules is a SIMM or DIMM.

15. A system comprising:

a memory controller adapted to output an address signal and a command signal and a select signal;

a plurality of memory modules; and

a bus adapted to transmit the address signal, the command signal and the select signal to each memory module,

wherein each of the memory modules includes a register adapted to receive and buffer the command signal and the address signal and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the select signal for accessing the memory devices.

16. The system of claim 15, wherein the register includes:

a buffer adapted to receive and buffer the command signal and the address signal;

a first latch connected to the buffer adapted to latch an output signal of the buffer, in response to the select signal; and

a second latch adapted to transmit an output signal of the first latch to the memory devices via a predetermined bus, in response to a clock signal.