Dual processor apparatus capable of burst concurrent writing of data

• US 20030204695A1
• Filed: 02/05/2003
• Published: 10/30/2003
• Est. Priority Date: 04/29/2002
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Joo-Yong, Choe, Byung-Gu
• Application Number:
  US10/358,225
• Publication Number:
  US 20030204695A1
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A dual processor apparatus is capable of burst concurrent writing of data during a burst cycle in a communication system including two processors, one of which is in active mode, when the other is in standby mode. The processor in standby mode is operated in dependence on the control of the processor in active mode. In the apparatus, the central processing unit of the processor in active mode generates a dual request signal and provides a burst cycle, which can continuously record n data blocks with one row address strobe signal and n column address strobe signals, thereby storing n data blocks in a dynamic memory inside of the processor during the burst cycle and transmitting the stored data and corresponding addresses to the processor in standby mode each time when the storing is executed; and the central processing unit of the processor in standby mode recognizes the start of burst cycle concurrent writing if a dual request signal and a burst signal are received from the processor in active mode, and stores the data received from the processor in active mode in a corresponding position in accordance with the addresses received from the processor in active mode. The apparatus enhances reliability and improves performance in connection with the demand for data communication control by a routing processor controller used in super-high speed communication networks or for dualization for a main controller used in various communication networks.

Claims

1. A dual processor apparatus capable of burst concurrent writing of data employed in a communication system, comprising:

two processors, one of said two processors being in active mode when the other is in standby mode, the processor in standby mode being operated in dependence on the control of the processor in active mode,

with a central processing unit of the processor in active mode generating a dual request signal and providing a burst cycle allowing n data blocks to be continuously recorded with one row address strobe signal and n column address strobe signals to accommodate a storing of n data blocks in a dynamic memory inside of the processor in active mode during said burst cycle and transmitting the stored data and a corresponding address to said processor in standby mode each time the storing is executed; and

with the central processing unit of said processor in standby mode recognizing the start of the burst cycle concurrent writing when a dual request signal and a burst signal are received from said processor in active mode, and storing said data received from said processor in active mode in a corresponding position in accordance with the addresses received from said processor in active mode.

2. The dual processor apparatus according to claim 1, with each time data is stored in said processor in standby mode, a bus and dynamic memory control section within said processor in standby mode generating a response signal and transmitting the response signal to said processor in active mode.

3. The dual processor apparatus according to claim 1, with each of said processors comprising:

a central processing unit recognizing a mode and generating a corresponding control signal;

a memory module of dynamic memory storing data;

a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory;

a first control buffer buffering the control signal generated from said bus and dynamic memory control section;

a first address buffer buffering an address generated from said bus and dynamic memory control section;

a first data buffer buffering the data generated from said bus and dynamic memory control section;

a second control buffer buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor, or for buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section;

a second data buffer buffering data outputted from said first data buffer and transferring the data to the counterpart processor, or for buffering data transferred from the counterpart processor and transferring the data to said dynamic memory; and

a dual request and response buffer buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor.

4. The dual processor apparatus according to claim 1, further comprising of continuously generating offset addresses in accordance with active side column address strobe.

5. The dual processor apparatus according to claim 1, with each of said processors comprising:

a central processing unit recognizing a mode and generating a corresponding control signal;

a memory module of dynamic memory storing data;

a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory;

a first control buffer buffering the control signal generated from said bus and dynamic memory control section;

a first address buffer buffering an address generated from said bus and dynamic memory control section; and

a first data buffer buffering the data generated from said bus and dynamic memory control section.

6. The dual processor apparatus according to claim 1, with each of said processors further comprising:

a second control buffer buffering the control signal outputted from a first control buffer to transfer the control signal to the counterpart processor, or for buffering an address transferred from the counterpart processor and transferring the address to a bus and dynamic memory control section; and

a second data buffer buffering data outputted from a first data buffer and transferring the data to the counterpart processor, or for buffering data transferred from the counterpart processor and transferring the data to a memory.

7. The dual processor apparatus according to claim 5, with each of said processors further comprising:

a dual request and response buffer buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor.

8. The dual processor apparatus according to claim 2, with each of said processors comprising:

a central processing unit recognizing a mode and generating a corresponding control signal;

a memory module of dynamic memory storing data;

a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory;

a first control buffer buffering the control signal generated from said bus and dynamic memory control section;

a first address buffer buffering an address generated from said bus and dynamic memory control section;

a first data buffer buffering the data generated from said bus and dynamic memory control section;

a second control buffer buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor, or for buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section;

a second data buffer buffering data outputted from said first data buffer and transferring the data to the counterpart processor, or for buffering data transferred from the counterpart processor and transferring the data to said dynamic memory; and

a dual request and response buffer buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor.

9. A method, comprising:

generating by a central processing unit of a processor in active mode, a dual request signal and providing a burst cycle allowing n data blocks to be continuously recorded with one row address strobe signal and n column address strobe signals to accommodate a storing of n data blocks in a dynamic memory inside of the processor in active mode during said burst cycle and transmitting the stored data and a corresponding address to a processor in standby mode each time the storing is executed, said processor in active mode and said processor in standby mode being at least two processors of a plurality of processors where one of said two processors being in active mode when the other is in standby mode, the processor in standby mode being operated in dependence on the control of the processor in active mode; and

recognizing by the central processing unit of said processor in standby mode, the start of the burst cycle concurrent writing when a dual request signal and a burst signal are received from said processor in active mode, and storing said data received from said processor in active mode in a corresponding position in accordance with the addresses received from said processor in active mode.

10. The method of claim 9, with each time data is stored in said processor in standby mode, a bus and dynamic memory control section within said processor in standby mode generating a response signal and transmitting the response signal to said processor in active mode.

11. The method of claim 9, with each of said processors comprising:

recognizing a mode and generating a corresponding control signal by a central processing unit;

storing data by a memory module of dynamic memory;

maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory by a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory;

buffering the control signal generated from said bus and dynamic memory control section by a first control buffer;

buffering an address generated from said bus and dynamic memory control section by a first address buffer;

buffering the data generated from said bus and dynamic memory control section by a first data buffer;

buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor by a second control buffer or buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section by said second control buffer;

buffering data outputted from said first data buffer and transferring the data to the counterpart processor by a second data buffer, or buffering data transferred from the counterpart processor and transferring the data to said dynamic memory by said second data buffer; and

buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor by a dual request and response buffer.

12. The method of claim 10, with each of said processors comprising:

recognizing a mode and generating a corresponding control signal by a central processing unit;

storing data by a memory module of dynamic memory;

maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory by a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory;

buffering the control signal generated from said bus and dynamic memory control section by a first control buffer;

buffering an address generated from said bus and dynamic memory control section by a first address buffer;

buffering the data generated from said bus and dynamic memory control section by a first data buffer;

buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor by a second control buffer or buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section by said second control buffer;

buffering data outputted from said first data buffer and transferring the data to the counterpart processor by a second data buffer, or buffering data transferred from the counterpart processor and transferring the data to said dynamic memory by said second data buffer; and

buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor by a dual request and response buffer.

13. The method of claim 9, with each of said processors comprising:

recognizing a mode and generating a corresponding control signal by a central processing unit;

storing data by a memory module of dynamic memory; and

maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory by a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory.

14. The method of claim 13, further comprising:

buffering the control signal generated from said bus and dynamic memory control section by a first control buffer;

buffering an address generated from said bus and dynamic memory control section by a first address buffer; and

buffering the data generated from said bus and dynamic memory control section by a first data buffer.

15. The method of claim 14, further comprising:

buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor by a second control buffer or buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section by said second control buffer; and

buffering data outputted from said first data buffer and transferring the data to the counterpart processor by a second data buffer, or buffering data transferred from the counterpart processor and transferring the data to said dynamic memory by said second data buffer.

16. The method of claim 14, further comprising of buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor by a dual request and response buffer.

17. An apparatus, comprising:

a plurality of processors with at least one of said plurality of processors being in active mode when at least a second processor is in standby mode, the processor in standby mode being operated in dependence on the control of the processor in active mode,

with a central processing unit of the processor in active mode generating a dual request signal and providing a burst cycle allowing n data blocks to be continuously recorded with one row address strobe signal and n column address strobe signals to accommodate a storing of n data blocks in a dynamic memory inside of the processor in active mode during said burst cycle and transmitting the stored data and a corresponding address to said processor in standby mode each time the storing is executed; and

with the central processing unit of said processor in standby mode recognizing the start of the burst cycle concurrent writing when a dual request signal and a burst signal are received from said processor in active mode, and storing said data received from said processor in active mode in a corresponding position in accordance with the addresses received from said processor in active mode.

18. The apparatus of claim 17, with each time data is stored in said processor in standby mode, a bus and dynamic memory control section within said processor in standby mode generating a response signal and transmitting the response signal to said processor in active mode.

19. The apparatus of claim 17, with each one of said processors comprising:

a central processing unit recognizing a mode and generating a corresponding control signal;

a memory module of dynamic memory storing data;

a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory;

a first control buffer buffering the control signal generated from said bus and dynamic memory control section;

a first address buffer buffering an address generated from said bus and dynamic memory control section;

a first data buffer buffering the data generated from said bus and dynamic memory control section;

a second control buffer buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor, or for buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section;

a second data buffer buffering data outputted from said first data buffer and transferring the data to the counterpart processor, or for buffering data transferred from the counterpart processor and transferring the data to said dynamic memory; and

a dual request and response buffer buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor.

20. The apparatus of claim 18, with each one of said processors comprising:

a central processing unit recognizing a mode and generating a corresponding control signal;

a memory module of dynamic memory storing data;

a bus and dynamic memory control section connected to said central processing unit with the bus and dynamic memory maintaining and implementing a burst cycle and causing burst cycle concurrent writing to be executed in said dynamic memory;

a first control buffer buffering the control signal generated from said bus and dynamic memory control section;

a first address buffer buffering an address generated from said bus and dynamic memory control section;

a first data buffer buffering the data generated from said bus and dynamic memory control section;

a second control buffer buffering the control signal outputted from said first control buffer to transfer the control signal to the counterpart processor, or for buffering an address transferred from the counterpart processor and transferring the address to said bus and dynamic memory control section;

a second data buffer buffering data outputted from said first data buffer and transferring the data to the counterpart processor, or for buffering data transferred from the counterpart processor and transferring the data to said dynamic memory; and

a dual request and response buffer buffering and transferring request and response signals for the burst cycle concurrent writing between said bus and dynamic memory control section and the counterpart processor.