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Dual processor apparatus capable of burst concurrent writing of data

  • US 20030204695A1
  • Filed: 02/05/2003
  • Published: 10/30/2003
  • Est. Priority Date: 04/29/2002
  • Status: Abandoned Application
First Claim
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1. A dual processor apparatus capable of burst concurrent writing of data employed in a communication system, comprising:

  • two processors, one of said two processors being in active mode when the other is in standby mode, the processor in standby mode being operated in dependence on the control of the processor in active mode, with a central processing unit of the processor in active mode generating a dual request signal and providing a burst cycle allowing n data blocks to be continuously recorded with one row address strobe signal and n column address strobe signals to accommodate a storing of n data blocks in a dynamic memory inside of the processor in active mode during said burst cycle and transmitting the stored data and a corresponding address to said processor in standby mode each time the storing is executed; and

    with the central processing unit of said processor in standby mode recognizing the start of the burst cycle concurrent writing when a dual request signal and a burst signal are received from said processor in active mode, and storing said data received from said processor in active mode in a corresponding position in accordance with the addresses received from said processor in active mode.

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