On-chip reset circuitry and method
First Claim
1. An integrated circuit comprising:
- an external reset input for receiving an external reset signal;
a clock input for receiving a clock signal; and
a reset signal sub-circuit connected to said external reset input and said clock input and including an internal reset output connected to other circuits of said integrated circuit, said reset signal sub-circuit immediately supplying an internal reset signal on said internal reset output to reset said other circuits upon receipt of said external reset signal and ceasing to supply said internal reset signal on said internal reset output upon a next clock signal received at said clock input following ceasing to receive said external reset signal at said external reset input.
1 Assignment
0 Petitions
Accused Products
Abstract
An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.
14 Citations
6 Claims
-
1. An integrated circuit comprising:
-
an external reset input for receiving an external reset signal;
a clock input for receiving a clock signal; and
a reset signal sub-circuit connected to said external reset input and said clock input and including an internal reset output connected to other circuits of said integrated circuit, said reset signal sub-circuit immediately supplying an internal reset signal on said internal reset output to reset said other circuits upon receipt of said external reset signal and ceasing to supply said internal reset signal on said internal reset output upon a next clock signal received at said clock input following ceasing to receive said external reset signal at said external reset input. - View Dependent Claims (2, 3, 4)
-
-
5. The method resetting an integrated circuit including combinational logic and sequential logic comprising the steps of:
-
asynchronously forcing combinational logic of the integrated circuit to a reset state upon receipt of an internal reset signal; and
synchronously forcing sequential logic of the integrated circuit to a reset state upon receipt of a next clock signal following receipt of said internal reset signal.
-
-
6. The method of claim 6, further including the steps of:
-
asynchronously supplying said internal reset signal upon receipt of an external reset signal; and
synchronously ending said internal reset signal upon a next clock signal following end of said external reset signal.
-
Specification