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On-chip reset circuitry and method

  • US 20030204713A1
  • Filed: 04/24/2003
  • Published: 10/30/2003
  • Est. Priority Date: 04/26/2002
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • an external reset input for receiving an external reset signal;

    a clock input for receiving a clock signal; and

    a reset signal sub-circuit connected to said external reset input and said clock input and including an internal reset output connected to other circuits of said integrated circuit, said reset signal sub-circuit immediately supplying an internal reset signal on said internal reset output to reset said other circuits upon receipt of said external reset signal and ceasing to supply said internal reset signal on said internal reset output upon a next clock signal received at said clock input following ceasing to receive said external reset signal at said external reset input.

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