Watchdog timer using a high precision event timer

• US 20030204792A1
• Filed: 04/25/2002
• Published: 10/30/2003
• Est. Priority Date: 04/25/2002
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Nelson, Eric Frank, Cahill, Jeremy Paul
• Granted Patent: US 7,689,875 B2
• Time in Patent Office: Days
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer. Thus, another software component can call and interact with the watchdog timer interface for a system event and view the watchdog timer interface as a watchdog timer (i.e., the operation of the hardware based timer is transparent).

Claims

1. A watchdog timer system comprising:

a hardware timer that periodically increments a counter value towards a compare value and that generates an interrupt on the compare value being equal to the counter value; and

a watchdog timer interface that configures the hardware timer to function as a watchdog timer.

2. The system of claim 1, further comprising an exception handler that is executed in response to the interrupt being generated and that performs error recovery procedures.

3. The system of claim 1, the watchdog timer interface sets the counter value to zero and the compare value to a computed value.

4. The system of claim 3, the compare value being a function of a timelength and a tick period.

5. The system of claim 1, the watchdog timer interface enables the hardware timer on receiving a start parameter.

6. The system of claim 1, the watchdog timer interface further sets the interrupt generated by the hardware timer as a desired interrupt.

7. The system of claim 1, the hardware timer being a 64 bit timer.

8. The system of claim 1, the hardware timer being a 32 bit timer.

9. The system of claim 1, the hardware timer being an up-counter.

10. The system of claim 1, the hardware timer being a down-counter.

11. The system of claim 1, the watchdog timer interface being at least partially implemented in kernel mode.

12. The system of claim 1, further comprising an application that calls the watchdog timer interface with a timelength parameter for a system event.

13. The system of claim 12, the system event being backing up a computer system.

14. The system of claim 12, the system event being communicating with a network server.

15. The system of claim 12, the application being a component of an operating system.

16. The system of claim 12, the application being a hardware abstraction layer.

17. The system of claim 2, the exception handler being a component of an operating system.

18. The system of claim 12, the application operative to call the watchdog timer interface with a reset parameter to avoid generation of the interrupt.

19. A method of operating a hardware timer as a watchdog timer comprising:

setting a compare value of the hardware timer to a computed value, the computed value being a function of a desired time out of a system event;

setting a counter value of the hardware timer to an initial value;

enabling the hardware timer;

incrementing the counter value every tick period; and

generating an interrupt on the compare value being equal to the counter value.

20. The method of claim 19, further comprising periodically resetting the hardware timer prior to the interrupt being generated.

21. The method of claim 20, the hardware timer being reset by disabling the hardware timer, setting the counter value to the initial value and enabling the hardware timer.

22. The method of claim 19, further comprising disabling the hardware timer on successful processing of the system event.

23. The method of claim 19, further comprising setting the interrupt to be a desired interrupt.

24. The method of claim 19, further comprising executing an exception handler triggered by the interrupt.

25. A method of detecting and handling errors utilizing a watchdog timer comprising:

setting a time length for a system event;

starting a watchdog timer system for the system event according to the time length, the watchdog timer system having a hardware timer controlled by a watchdog timer interface;

resetting the watchdog timer system during successful processing of the event;

halting the watchdog timer system on successful processing to the system event; and

generating an interrupt on the timer expiring.

26. The method of claim 25, further comprising handling failure of the system event on the interrupt being generated.

27. A data packet comprising:

information associated with a watchdog timer interface, the information comprising parameters of a hardware timer and controlled by the watchdog timer interface.

28. A computer readable medium storing computer executable instructions of components operable to perform a method of operating a hardware timer as a watchdog timer, comprising:

a component for setting a compare value of the hardware timer to a computed value, the computed value being a function of a desired time out of a system event;

a component for setting a counter value of the hardware timer to an initial value;

a component for enabling the hardware timer;

a component for incrementing the counter value every tick period; and

a component for generating an interrupt on the compare value being equal to the counter value.

29. A computing system comprising:

at least three hardware timers; and

a watchdog timer interface that configures at least one of the hardware timers to function as a watchdog timer.

30. A computing system comprising:

a plurality of hardware timers; and

means for configuring at least one of the hardware timers to operate as a watchdog timer.