Watchdog timer using a high precision event timer
First Claim
1. A watchdog timer system comprising:
- a hardware timer that periodically increments a counter value towards a compare value and that generates an interrupt on the compare value being equal to the counter value; and
a watchdog timer interface that configures the hardware timer to function as a watchdog timer.
2 Assignments
0 Petitions
Accused Products
Abstract
A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer. Thus, another software component can call and interact with the watchdog timer interface for a system event and view the watchdog timer interface as a watchdog timer (i.e., the operation of the hardware based timer is transparent).
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Citations
30 Claims
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1. A watchdog timer system comprising:
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a hardware timer that periodically increments a counter value towards a compare value and that generates an interrupt on the compare value being equal to the counter value; and
a watchdog timer interface that configures the hardware timer to function as a watchdog timer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of operating a hardware timer as a watchdog timer comprising:
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setting a compare value of the hardware timer to a computed value, the computed value being a function of a desired time out of a system event;
setting a counter value of the hardware timer to an initial value;
enabling the hardware timer;
incrementing the counter value every tick period; and
generating an interrupt on the compare value being equal to the counter value. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A method of detecting and handling errors utilizing a watchdog timer comprising:
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setting a time length for a system event;
starting a watchdog timer system for the system event according to the time length, the watchdog timer system having a hardware timer controlled by a watchdog timer interface;
resetting the watchdog timer system during successful processing of the event;
halting the watchdog timer system on successful processing to the system event; and
generating an interrupt on the timer expiring. - View Dependent Claims (26)
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27. A data packet comprising:
information associated with a watchdog timer interface, the information comprising parameters of a hardware timer and controlled by the watchdog timer interface.
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28. A computer readable medium storing computer executable instructions of components operable to perform a method of operating a hardware timer as a watchdog timer, comprising:
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a component for setting a compare value of the hardware timer to a computed value, the computed value being a function of a desired time out of a system event;
a component for setting a counter value of the hardware timer to an initial value;
a component for enabling the hardware timer;
a component for incrementing the counter value every tick period; and
a component for generating an interrupt on the compare value being equal to the counter value.
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29. A computing system comprising:
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at least three hardware timers; and
a watchdog timer interface that configures at least one of the hardware timers to function as a watchdog timer.
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30. A computing system comprising:
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a plurality of hardware timers; and
means for configuring at least one of the hardware timers to operate as a watchdog timer.
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Specification