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Memory testing device and method

  • US 20030204797A1
  • Filed: 06/13/2002
  • Published: 10/30/2003
  • Est. Priority Date: 04/24/2002
  • Status: Active Grant
First Claim
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1. A memory testing apparatus for testing at least one memory device, comprising:

  • a waveform-shaping module configured to generate a test signal according to an address signal and to output the test signal to the memory device;

    a comparing module configured to compare an expected value with an output signal received from the memory device in response to the test signal, and to output a comparison result;

    an address-compressing module configured to generate a compressed address for the comparison result; and

    an error catch memory configured to record the comparison result in a memory location of the error catch memory according to the compressed address.

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