Memory testing device and method

• US 20030204797A1
• Filed: 06/13/2002
• Published: 10/30/2003
• Est. Priority Date: 04/24/2002
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lin, Wen-Hsi
• Granted Patent: US 7,243,273 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

A memory testing apparatus rapidly tests memory devices with a relatively small error catch memory. The memory testing apparatus provides an address compressing module that minimizes an amount of error catch memory necessary to test one or more memory devices. The memory testing apparatus further divides each of the memory devices into a plurality of areas, and tests each area sequentially until a bit failure is detected in the area thereby attenuating testing time.

Claims

1. A memory testing apparatus for testing at least one memory device, comprising:

a waveform-shaping module configured to generate a test signal according to an address signal and to output the test signal to the memory device;

a comparing module configured to compare an expected value with an output signal received from the memory device in response to the test signal, and to output a comparison result;

an address-compressing module configured to generate a compressed address for the comparison result; and

an error catch memory configured to record the comparison result in a memory location of the error catch memory according to the compressed address.

2. The memory testing apparatus of claim 1, wherein the comparison result is recorded in a single bit of the error catch memory.

3. The memory testing apparatus of claim 1, wherein the compressed address points to a bit of the error catch memory.

4. The memory testing apparatus of claim 1, wherein:

the test signal comprises a data signal;

the output signal corresponds to an area of the memory device that was written with the data signal and then read from; and

the compressed address maps the area of the memory device to an area of the error catch memory.

5. The memory testing apparatus of claim 4, wherein:

the area of the memory device comprises a plurality of bits; and

the area of the error catch memory is one bit.

6. The memory testing apparatus of claim 1, wherein:

the compressed address maps an area of the memory device to an area of the error catch memory; and

the area of the memory device is greater than the area of the error catch memory.

7. The memory testing apparatus of claim 6, wherein:

the area of the memory device comprises a plurality of bits; and

the area of the error catch memory is one bit.

8. The memory testing apparatus of claim 1, wherein:

the test signal comprises a data signal which is equal to the expected value;

a number of bits of the data signal is equal to a number of bits of the output signal; and

the comparing module is configured to sequentially compare bits of the output signal with corresponding bits of the expected value, the comparing module being configured to stop comparing the bits of the output signal and the expected value when a mismatch is detected between a bit of the output signal and a corresponding bit of the expected value, the mismatch indicating a failed memory location of the memory device.

9. The memory testing apparatus of claim 1, wherein the error catch memory is configured to record the comparison result in a memory location of the error catch memory according to the compressed address only when the comparison result is indicative of a mismatch between the output signal and the expected value.

10. The memory testing apparatus of claim 1, wherein:

the test signal includes the expected value;

the address compressing module uses the address signal to generate the compressed address;

the memory testing apparatus further comprises a pattern-generating module that is configured to generate and output the address signal and the expected value;

the address signal points to a cell area of the memory device;

when one or more bits of the expected value and the output signal are mismatched, the comparing module stops comparing and outputs the comparison result as a “

fail”

; and

when the expected value and the corresponding output signal are matched, the comparing module outputs the comparison result as a “

pass.”

11. The memory testing apparatus of claim 1, wherein the at least one memory device comprises a plurality of memory devices, and wherein:

the waveform-shaping module generates a plurality of test signals according to a plurality of address signals, and outputs each of the plurality of test signals to one of the plurality of memory devices;

the comparing module compares expected values corresponding to the test signals with output signals from corresponding memory devices, and outputs a plurality of comparison results;

the address-compressing module generates compressed addresses for the plurality of comparison results; and

the error catch memory records a plurality of the comparison results in a corresponding plurality of memory locations of the error catch memory according to a corresponding plurality of the compressed addresses.

12. The memory testing apparatus of claim 1, wherein:

the at least one memory device comprises a plurality of memory devices; and

the error catch memory comprises a plurality of divisions corresponding to the plurality of memory devices, each division storing comparison results indicative of failed areas of a corresponding one of the plurality of memory devices.

13. The memory testing apparatus of claim 12, wherein each comparison result is recorded in a single bit of the error catch memory.

14. A memory testing apparatus for testing at least one memory device, comprising:

a waveform-shaping module configured to output a test signal to the memory device; and

a comparing module configured to sequentially compare bits of an output signal, received from the memory device in response to the test signal, with corresponding bits of an expected value, the comparing module being configured to stop comparing the bits of the output signal and the expected value when a mismatch is detected between a bit of the output signal and a corresponding bit of the expected value, the mismatch indicating a failed memory location of the memory device.

15. The memory testing apparatus of claim 14, wherein, following detection of a mismatch, the waveform-shaping module outputs another test signal to the memory device, and the comparing module sequentially compares bits of another output signal, received from the memory device in response to the other test signal, with corresponding bits of another expected value.

16. The memory testing apparatus of claim 15, wherein:

the test signal includes an address signal that points to a cell area of the memory device; and

following the detection of a mismatch, the address signal is changed to point to another cell area of the memory device.

17. The memory testing apparatus of claim 16, wherein:

the comparing module is configured to output a comparison result upon detection of a mismatch; and

the memory testing apparatus further comprises;

(a) an address-compressing module configured to generate a compressed address for the comparison result; and

(b) an error catch memory configured to record the comparison result in a memory location of the error catch memory according to the compressed address.

18. The memory testing apparatus of claim 17, wherein:

the compressed address points to a bit of the error catch memory; and

the comparison result is stored in the bit of the error catch memory.

19. The memory testing apparatus of claim 18, wherein:

the memory device comprises a plurality of cell areas, with each cell area comprising a plurality of bits; and

a number of bits of the expected value is equal to a number of bits of the output signal.

20. The memory testing apparatus of claim 14, wherein the at least one memory device comprises a plurality of memory devices, and wherein:

the waveform-shaping module is configured to generate a plurality of test signals, the test signals comprising a plurality of address signals and a plurality of expected values, each of the plurality of address signals pointing to an area of a corresponding one of the memory devices, the waveform-shaping module further being configured to output the test signals to the memory devices;

the comparing module is configured to compare the expected values with output signals from the memory devices, which are received from the memory devices in response to the test signals, and the comparing module being configured to output comparison results;

the memory testing apparatus further comprises an address-compressing module that is configured to generate compressed addresses for the comparison results, using corresponding address signals; and

the memory testing apparatus further comprises an error catch memory that is configured to receive comparison results and record a plurality of them in a corresponding plurality of memory locations of the error catch memory according to a corresponding plurality of the compressed addresses.

21. A memory testing method for testing at least one memory device, comprising:

generate a test signal according to an address signal;

outputting the test signal to the memory device;

comparing an expected value with an output signal received from the memory device in response to the test signal;

outputting a comparison result;

generating a compressed address for the comparison result; and

recording the comparison result in a memory location of an error catch memory according to the compressed address.

22. The memory testing method of claim 21, wherein:

the test signal comprises a data signal;

the output signal corresponds to an area of the memory device that was written with the data signal and then read from; and

the compressed address maps the area of the memory device to an area of the error catch memory, which is smaller than the area of the memory device.

23. The memory testing method of claim 21, wherein:

the test signal comprises a data signal which is equal to the expected value;

a number of bits of the data signal is equal to a number of bits of the output signal; and

the comparing includes sequentially comparing bits of the output signal with corresponding bits of the expected value, until (1) all bits of the output signal have been compared or (2) a mismatch is detected between a bit of the output signal and a corresponding bit of the expected value, the mismatch indicating a failed memory location of the memory device.

24. The memory testing method of claim 21, wherein the at least one memory device comprises a plurality of memory devices, and wherein:

the test-signal generating includes generating a plurality of test signals according to a plurality of address signals;

the test-signal outputting includes outputting each of the plurality of test signals to one of the plurality of memory devices;

the comparing includes comparing expected values corresponding to the test signals with output signals from corresponding memory devices;

the comparison-result outputting includes outputting comparison results;

the compressed-address generating includes generating compressed addresses for the comparison results; and

the error catch memory records a plurality of the comparison results in a corresponding plurality of memory locations of the error catch memory according to a corresponding plurality of the compressed addresses.

25. The memory testing method of claim 21, wherein the error catch memory records the comparison result in a memory location of the error catch memory according to the compressed address only when the comparison result is indicative of a mismatch between the output signal and the expected value.

26. The memory testing method of claim 21, wherein:

the test signal includes the expected value;

the address signal is used to generate the compressed address;

the address signal points to a cell area of the memory device;

when the expected value and the corresponding output signal are mismatched, the comparing stops and a “

fail”

comparison result is outputted; and

when the expected value and the corresponding output signal are matched, a “

pass”

comparison result is outputted.

27. A memory testing method for testing at least one memory device, comprising:

outputting a test signal to the memory device; and

sequentially comparing bits of an output signal, received from the memory device in response to the test signal, with corresponding bits of an expected value, the comparing of bits of the output signal and the expected value being halted when a mismatch is detected between a bit of the output signal and a corresponding bit of the expected value, the mismatch indicating a failed memory location of the memory device.

28. The memory testing method of claim 27, wherein following detection of a mismatch, another test signal is outputted to the memory device, and bits of another output signal, which is received from the memory device in response to the other test signal, are sequentially compared with corresponding bits of another expected value.

29. The memory testing method of claim 28, and further comprising:

outputting a comparison result upon detection of a mismatch;

generating a compressed address for the comparison result; and

recording the comparison result in a memory location of an error catch memory according to the compressed address.

30. The memory testing method of claim 29, wherein:

the memory device comprises a plurality of cell areas, with each cell area comprising a plurality of bits;

the compressed address points to a bit of the error catch memory; and

the comparison result is stored in the bit of the error catch memory.

31. The memory testing method of claim 27, wherein the at least one memory device comprises a plurality of memory devices, and wherein:

the outputting is preceded with generating a plurality of test signals, the test signals comprising a plurality of address signals and a plurality of expected values, each of the plurality of address signals pointing to an area of a corresponding one of the memory devices, and the outputting including outputting the test signals to the memory devices;

the comparing includes comparing the expected values with output signals received from the memory devices in response to the test signals, and is followed with outputting comparison results;

the memory testing method includes generating compressed addresses for the comparison results, using corresponding address signals; and

the memory testing method further includes recording a plurality of the comparison results in a corresponding plurality of memory locations of an error catch memory according to a corresponding plurality of the compressed addresses.