Method and apparatus for wafer-level burn-in and testing of integrated circuits

• US 20030205737A1
• Filed: 05/27/2003
• Published: 11/06/2003
• Est. Priority Date: 04/25/2000
• Status: Active Grant

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L., Fenner, Andreas A.
• Granted Patent: US 6,806,494 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence

Abstract

In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Claims

1. A system for reducing test time for integrated circuits on a wafer, the system comprising:

means for powering up all die on the wafer, means for stabilizing the integrated circuits; and

means for testing each die;

said means for powering, said means for stabilizing, and said means for testing being controlled by a circuit and being operable in a respective sequence.

2. The system of claim 1 wherein said means for testing includes means for indexing a test probe from one die to the next.

3. A method of testing integrated circuits on a wafer, the method comprising:

powering up all die on the wafer;

stabilizing said all die on the wafer; and

indexing a wafer tester from one die to a next thereby testing said all die on the wafer.

4. The method of claim 3 wherein said powering up includes supplying power to said all die in parallel.

5. The method of claim 3 wherein said indexing includes immediately testing a die next to one that has been contemporaneously tested.

6. A software system implemented to reduce test time for integrated circuits in a wafer, the software system comprising:

means for confirming that all die on the wafer are powered up;

means for confirming that all die on the wafer are powered up;

means for confirming that said die on the wafer are stabilized subsequent to being powered up; and

means for indexing a wafer tester from one die to another until all said die have been tested.

7. The software system of claim 6 wherein said means for confirming if said all die on the wafer are powered up includes controlling circuitry to power said all die in parallel.

8. The software system of claim 6 wherein said means for confirming if said all die on the wafer are stabilized includes logic means to initiate indexing said wafer tester if and only if said all die are stabilized.

9. The software system of claim 6 wherein said means for indexing includes logic means to end moving the wafer tester if and only if said all die are tested.