Semiconductor device with an L-shaped/reversed L-shaped gate side-wall insulating film

• US 20030205774A1
• Filed: 04/25/2003
• Published: 11/06/2003
• Est. Priority Date: 12/27/2000
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hokazono, Akira
• Granted Patent: US 6,956,276 B2
• Time in Patent Office: Days
• US Class Current: 257/486
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Provided is a semiconductor device, comprising a gate electrode formed on a semiconductor substrate, source/drain diffusion layers formed on both sides of the gate electrode, a gate electrode side-wall on the side of the source/drain diffusion layer and a gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode and having an L-shaped/reversed L-shaped cross-sectional shape, and a semiconductor layer extending over the gate side-wall insulating film covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode.

Claims

1. A semiconductor device, comprising:

a gate electrode formed on a surface region of a semiconductor substrate;

a source region and a drain region which are formed in the surface region of the semiconductor substrate on both sides of the gate electrode;

a gate side-wall insulating film having a first portion covering a side-wall of the gate electrode on the side of each of the source region and the drain region and a second portion covering a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode; and

a silicon containing layer containing silicon formed on each of the source region and the drain region, the silicon containing layer covering each of the source region and the drain region.

2. A semiconductor device according to claim 1, further comprising a buried device isolation region comprising a trench contiguous to the outer peripheral edge portion of each of the source region and the drain region and having an insulating film buried therein.

3. A semiconductor device according to claim 1, wherein the silicon containing layer is a Si layer or a SiGe layer, and the silicon layer includes a silicide layer formed in the surface region.

4. A semiconductor device according to claim 2, wherein the silicon containing layer is a Si layer or a SiGe layer, and the Si layer or the SiGe layer includes a silicide layer formed in the surface region.

5. A semiconductor device according to claim 1, wherein the silicon containing layer is connected to a contact plug.

6. A semiconductor device according to claim 2, wherein the silicon containing layer is connected to a contact plug.

7. A semiconductor device according to claim 3, wherein the silicon containing layer is connected to a contact plug.

10. A semiconductor device according to claim 1, wherein the gate side wall insulating film is made of SiN.

11. A semiconductor device according to claim 1, wherein the silicon containing layer is a silicide layer.

15. A semiconductor device according to claim 2, wherein an upper surface of the insulating film comprises an SiO₂ film.

16. A semiconductor device according to claim 2, wherein an upper surface of the insulating film is higher than that of the semiconductor substrate.

8. A semiconductor device comprising:

a gate electrode formed on an upper surface of a semiconductor substrate;

a source region and a drain region which are formed on both sides of the gate electrode;

a gate side-wall insulating film covering a side wall of the gate electrode on the side of each of the source region and the drain region and a part of the upper surface of the semiconductor substrate in the vicinity of the gate electrode;

a silicon containing layer formed on each of the source region and the drain region, the silicon containing layer covering each of the source region and the drain region; and

a buried device isolation region comprising a trench contiguous to the outer peripheral edge portion of each of the source region and the drain region and having an insulating film buried therein,

wherein the buried device isolation region includes;

a trench formed in an upper surface of a semiconductor substrate;

a first buried insulating film formed to extend along the inner wall of the trench in a manner to be buried in a lower portion of the trench to reach a predetermined depth from the open surface of the trench; and

a second buried insulating film formed to cover said first buried insulating film in an upper portion of the trench.

9. A semiconductor device according to claim 8, wherein the predetermined depth from the open surface of the trench is smaller than the minimum diameter of the open portion of the trench.

17. A semiconductor device according device according to claim 8, wherein the gate side-wall insulating film is made of SiN.

18. A semiconductor device according to claim 8, wherein the silicon containing layer is a silicide layer.

19. A semiconductor device according to claim 18, wherein the silicide layer includes a nickel silicone layer.

20. A semiconductor device according to claim 18, wherein the silicide layer includes a cobalt silicide layer.

21. A semiconductor device according to claim 18, wherein the silicide layer includes a titanium silicide layer.

22. A semiconductor device according to claim 8, wherein an upper surface of the insulating film comprises an SiO₂ film.

23. A semiconductor device according to claim 8, wherein an upper surface of the insulating film is higher than that of the semiconductor substrate.

12. A semiconductor device according to claim 12, wherein the silicide layer includes a nickel silicide layer.

13. A semiconductor device according to claim 12, wherein the silicide layer includes a cobalt silicide layer.

14. A semiconductor device according to claim 12, wherein the silicide layer includes a titanium silicide layer.