Multiple chips bonded to packaging structure with low noise and multiple selectable functions
First Claim
Patent Images
1. A method of forming a chip package for a semiconductor chip including the steps as follows:
- forming a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from;
a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board, forming solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection, providing a bypass capacitor with a first terminal and a second terminal, and connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure.
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Abstract
A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.
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Citations
44 Claims
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1. A method of forming a chip package for a semiconductor chip including the steps as follows:
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forming a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from;
a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board, forming solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection, providing a bypass capacitor with a first terminal and a second terminal, and connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure. - View Dependent Claims (2, 3, 4, 5)
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6. A package for semiconductor chips including:
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a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which are selected from;
a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board, solder connections between the printed circuit board and a chip overlying the printed circuit board in a flip chip connection, a bypass capacitor with a first terminal and a second terminal, and the first terminal of the bypass capacitor being connected to the power structure and the second terminal being connected to the ground structure. - View Dependent Claims (7, 8, 9, 10)
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11. A method of forming a chip package for a semiconductor chip including the steps as follows:
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forming a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board, forming a second printed circuit board having a top surface and a bottom surface, bonding a first chip to the top surface of the first printed circuit board and bonding a second chip to the bottom surface of the first printed circuit board in a flip chip connection, bonding a third chip to the bottom surface of the second printed circuit board in a flip chip connection, and bonding the chips to the printed circuit boards by means selected from the following;
a) solder balls, and b) gold bumps. - View Dependent Claims (12, 13, 14, 15, 20)
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16. A chip package for a semiconductor chip including:
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a first printed circuit board having a top surface and a bottom surface including a power plane and a ground plane located within the first printed circuit board, a second printed circuit board having a top surface and a bottom surface, a first chip bonded to the top surface of the first printed circuit board and a second chip bonded to the bottom surface of the first printed circuit board in a flip chip connection, a third chip bonded to the bottom surface of the second printed circuit board in a flip chip connection, a bypass capacitor with a first terminal and a second terminal, the first terminal of the bypass capacitor connected to the power plane and the second terminal of the bypass capacitor connected to the ground plane, and the bottom surface of the first printed circuit board interconnected to the top surface of the second printed circuit board with a solder ball. - View Dependent Claims (17, 18, 19)
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21. A method of forming a chip package for semiconductor chips including the steps as follows:
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forming a printed circuit board with a window therethrough having a length and a width and a top surface and a bottom surface, semiconductor chips including a primary chip and a secondary chip, forming bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window, locating the secondary chip suspended within the window and forming bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection. - View Dependent Claims (22, 23, 24, 31, 33, 34, 36)
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25. A chip package for semiconductor chips including the steps as follows:
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a printed circuit board with a window therethrough having a length and a width and a top surface and a bottom surface, semiconductor chips including a primary chip and a secondary chip, bonded connections between the top surface of the printed circuit board and the primary chip, with the primary chip overlying the window and which extends transversely across the width of the window, the secondary chip being suspended within the window and having bonded connections between the secondary semiconductor chip and the primary chip in a chip-on-chip connection. - View Dependent Claims (26, 27, 28)
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29. A method of forming a chip package for semiconductor chips including the steps as follows:
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providing a substrate having a top surface and a bottom surface, semiconductor chips including a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface, forming bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and forming bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving space between the secondary chip and the printed circuit board. - View Dependent Claims (30)
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32. A chip package for semiconductor chips including:
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a substrate having a top surface and a bottom surface, semiconductor chips including a primary chip and a secondary chip, the primary chip having a bottom surface and the secondary chip having a top surface, bonded chip-on-chip connections between the top surface of the secondary chip and the bottom surface of the primary chip, and bonded connections between the top surface of the substrate and the primary chip aside from the secondary chip leaving space between the secondary chip and the printed circuit board.
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35. A method of interconnected semiconductor chips including the steps as follows:
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semiconductor chips including a primary chip and a secondary chip, the primary chip having a top surface and the secondary chip having a bottom surface, forming bonded chip-on-chip connections between the bottom surface of the secondary chip and the top surface of the primary chip, and forming bonded connections between the top surface of the primary chip aside from the secondary chip.
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37. A pair of interconnected semiconductor chips comprising:
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a primary chip and a secondary chip, the primary chip having a top surface and the secondary chip having a bottom surface, bonded chip-on-chip connections between the bottom surface of the secondary chip and the top surface of the primary chip, and bonded connections between the top surface of the primary chip aside from the secondary chip. - View Dependent Claims (38)
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39. A method of forming a chip package for semiconductor chips comprising:
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forming a printed circuit board with a top surface and a window therethrough, connecting at least two primary semiconductor chips each of which only partially overlies the window to the top surface of a printed circuit board by solder connections, connecting a secondary semiconductor chip located within the window to at least of the two primary chips overlying the window in a chip-on-chip connection. - View Dependent Claims (40)
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41. A chip package for semiconductor chips comprising:
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a printed circuit board with a top surface and a window therethrough, at least two primary semiconductor chips each of which only partially overlies the window connected to the top surface of the printed circuit board by solder connections, a suspended secondary semiconductor chip located within the window, and the suspended semiconductor chip being connected to at least of the two primary chips overlying the window in a chip-on-chip connection. - View Dependent Claims (42)
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43. A method of forming a chip package for a semiconductor chip including the steps as follows:
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forming a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which include;
a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board, forming solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections, providing a bypass capacitor with a first terminal and a second terminal, and connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure, and forming optional pads for connection to optional solder balls for functional selection.
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44. A chip package for a semiconductor chip including:
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a printed circuit board having a top surface and a bottom surface including a power structure and a ground structure which include;
a) a power bus and a ground bus, and b) a power plane and a ground plane located within the printed circuit board, solder connections between the printed circuit board and a plurality of chips overlying the printed circuit board in flip chip connections, a bypass capacitor with a first terminal and a second terminal, and connecting the first terminal of the bypass capacitor to the power structure and connecting the second terminal of the bypass capacitor to the ground structure, and optional pads for connection to optional solder balls for functional selection.
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Specification