COARSE CALIBRATION CIRCUIT USING VARIABLE STEP SIZES TO REDUCE JITTER AND A DYNAMIC COURSE CALIBRATION (DCC) CIRCUIT FOR A 2 GHZ VCO

• US 20030206042A1
• Filed: 05/06/2002
• Published: 11/06/2003
• Est. Priority Date: 05/06/2002
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Walker, Norman Hugo, Mullgrav, Allan Leslie Jr., Sorna, Michael A., Moy, Victor
• Granted Patent: US 6,661,267 B2
• Time in Patent Office: Days
• US Class Current: 327/156
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/102 the additional signal being directly applied to the controlled loop oscillator
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

A calibration system for a Phase Locked Loop (PLL) includes a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency. A charge pump is connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter. The low pass filter provides a filtered error signal to the VCO and to a comparator system. The comparator system provides a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit. A calibration means continuously provides incremental calibration inputs to the VCO after a time delay. Thus the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.

Claims

1. A calibration system for a Phase Locked Loop (PLL) comprising:

a low pass filter for providing a filtered error signal to a voltage controlled oscillator (VCO) and a comparator system,

the comparator system providing an overlimit output indicating when the polarity of the error signal exceeds a positive limit or a negative limit, and

a calibration means for providing incremental calibration input to the VCO after a time delay,

whereby the frequency of the VCO in the PLL is corrected to compensate for frequency drift without jitter.

2. A calibration system in accordance with claim 1 wherein the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator.

3. A calibration system in accordance with claim 1 wherein the calibration means determines when an overlimit output has been received and then adjusts the calibration input.

4. A calibration system in accordance with claim 1 wherein:

the comparator system includes a high error comparator, a low error comparator and a positive error output, and

the calibration means samples the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input.

5. A calibration system in accordance with claim 1 wherein:

the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator, and

the calibration means samples the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time.

6. A calibration system in accordance with claim 1 wherein:

the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator,

the calibration means begins a calibration cycle by sampling the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time, and

the calibration means determining whether the calibration has corrected a detected error and repeating the correction cycle until correction of the error has been detected followed by returning to the beginning of the calibration cycle.

7. A calibration system in accordance with claim 6 wherein the calibration means includes a Dynamic Course Correction (DCC) circuit and a Digital to Analog (DAC) converter.

8. A calibration system in accordance with claim 7 wherein the Digital to Analog (DAC) converter includes means delaying the rate of change of incremental calibration input to the VCO.

9. A calibration system in accordance with claim 6 wherein:

the VCO comprises a voltage to current (V-I) converter connected to provide an input to a current controlled oscillator (ICO),

the calibration means includes a Dynamic Course Correction (DCC) circuit and a Digital to Analog Converter (DAC) and the DAC provides an input to the ICO.

10. A calibration system in accordance with claim 9 wherein the DAC includes means delaying the rate of change of incremental calibration input to the ICO.

11. A calibration system for a Phase Locked Loop (PLL) comprising:

a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency,

a charge pump connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter,

the low pass filter providing a filtered error signal to the VCO and to a comparator system,

the comparator system providing a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit, and

a calibration means for continuously providing incremental calibration input to the VCO after a time delay,

whereby the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs.

12. A calibration system in accordance with claim 11 wherein the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator.

13. A calibration system in accordance with claim 11 wherein the calibration means determines when an overlimit output has been received and then adjusts the calibration input.

14. A calibration system in accordance with claim 11 wherein:

the comparator system includes a high error comparator, a low error comparator and a positive error output, and

the calibration means samples the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input.

15. A calibration system in accordance with claim 11 wherein:

the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator, and

the calibration means samples the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time.

16. A calibration system in accordance with claim 11 wherein:

the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator,

the calibration means begins a calibration cycle by sampling the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time, and

the calibration means determining whether the calibration has corrected a detected error and repeating the correction cycle until correction of the error has been detected followed by returning to the beginning of the calibration cycle.

17. A calibration system in accordance with claim 16 wherein the calibration means includes a Dynamic Course Correction (DCC) circuit and a Digital to Analog (DAC) converter.

18. A calibration system in accordance with claim 17 wherein the Digital to Analog (DAC) converter includes means delaying the rate of change of incremental calibration input to the VCO.

19. A calibration system for a Phase Locked Loop (PLL) comprising:

a phase/frequency detector coupled to the output of a voltage controlled oscillator (VCO) and to a source of a reference frequency, the VCO comprising a voltage to current (V-I) converter connected to provide an input to a current controlled oscillator (ICO),

a charge pump connected to receive an error signal from the phase/frequency detector and provide a voltage to a low pass filter,

the low pass filter providing a filtered error signal to the VCO and to a comparator system,

the comparator system providing a comparator output indicating when the polarity of the error signal exceeds a positive limit or a negative limit,

a calibration means for continuously providing incremental calibration input to the VCO after a time delay, the calibration means including a Dynamic Course Correction (DCC) circuit and a Digital to Analog Converter (DAC) and the DAC provides an input to the ICO,

the calibration means begins a calibration cycle by sampling the output of the comparator system at sampling times and then determines when an overlimit output has been received and then adjusts the calibration input by a small increment followed by powering down the comparator system for a delay time, and

the calibration means determining whether the calibration has corrected a detected error and repeating the correction cycle until correction of the error has been detected followed by returning to the beginning of the calibration cycle,

whereby the frequency of the VCO in the PLL is continuously corrected to compensate for frequency drift and avoid jitter caused by an excessive rate of response to calibration inputs. the comparator system includes a high error comparator, a low error comparator and a positive-negative error comparator.

20. A calibration system in accordance with claim 19 wherein the DAC includes means delaying the rate of change of incremental calibration input to the ICO.