Operational amplifier circuit

• US 20030206060A1
• Filed: 06/04/2003
• Published: 11/06/2003
• Est. Priority Date: 05/16/2000
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Hisao
• Granted Patent: US 6,794,940 B2
• Time in Patent Office: Days
• US Class Current: 330/252
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 3/3027 using a common source driving stage, i.e. inverting stage
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45219 Folded cascode stages
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series
• CPC Class Codes: H03F 3/45699 Measuring at the input circuit of the differential amplifier
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45717 Controlling the loading circuit of the differential amplifier

Abstract

An operational amplifier circuit includes a first differential pair, which includes first and second transistors, and a second differential pair, which includes third and fourth transistors. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source is connected to the first differential pair to provide a first bias current. A second current source is connected to the second differential pair to provide a second bias current. A third current source is connected to the fifth transistor to provide a third bias current. A fourth current source is connected to the sixth transistor provide a fourth bias current. A control circuit controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

Claims

1. An operational amplifier circuit comprising:

a first differential pair including a first transistor responsive to a first input voltage and a second transistor responsive to a second input voltage;

a second differential pair including a third transistor responsive to the first input voltage and a fourth transistor responsive to the second input voltage;

a fifth transistor connected to the first and third transistors;

a sixth transistor connected to the second and fourth transistors;

a first current source, which is connected to the first differential pair, for supplying a first bias current to the first differential pair;

a second current source, which is connected to the second differential pair, for supplying a second bias current to the second differential pair;

a third current source, which is connected to the fifth transistor, for supplying a third bias current to the fifth transistor;

a fourth current source, which is connected to the sixth transistor, for supplying a fourth bias current to the sixth transistor; and

a control circuit, which is connected to the first to fourth current sources, for receiving the first and second input voltages and controlling the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

2. The operational amplifier circuit according to claim 1, wherein the control circuit includes:

a constant current source for producing a constant current that is equal to the sum of the first and second bias currents; and

a distribution circuit, which is connected to the first to fourth current sources, for comparing the first and second input voltages with a reference voltage and distributing the constant current of the constant current source to the first bias current of the first current source and the second to fourth bias currents of the second to fourth current sources based on a comparison result.

3. The operational amplifier circuit according to claim 1, wherein the first and third transistors are connected to each other, the fifth transistor is connected to a node between the first and third transistors, the second and fourth transistors are connected to each other, and the sixth transistor is connected to a node between the second and fourth transistors.

4. The operational amplifier circuit according to claim 3, wherein each of the first and second transistors is a P channel transistor and each of the third to sixth transistors is an N channel transistor.

5. The operational amplifier circuit according to claim 4, wherein each of the first, third and fourth current sources includes a P channel transistor and the second current source includes an N channel transistor.

6. The operational amplifier circuit according to claim 3, wherein at least one of the first and second transistors is a PNP bipolar transistor, and at least one of the third to sixth transistors is an NPN bipolar transistor.

7. An operational amplifier circuit comprising:

a first differential pair including a first transistor responsive to a first input voltage and a second transistor responsive to a second input voltage;

a second differential pair including a third transistor responsive to the first input voltage and a fourth transistor responsive to the second input voltage;

a first resistor element connected to the first and third transistors;

a second resistor element connected to the second and fourth transistors;

a first current source, which is connected to the first differential pair, for supplying a first bias current to the first differential pair;

a second current source, which is connected to the second differential pair, for supplying a second bias current to the second differential pair;

a third current source, which is connected to the first resistor element, for supplying a third bias current to the first resistor element;

a fourth current source, which is connected to the second resistor element, for supplying a fourth bias current to the second resistor element; and

a control circuit, which is connected to the first to fourth current sources, for receiving the first and second input voltages and controlling the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

8. A method of controlling first and second bias currents respectively supplied to first and second differential pairs of an operational amplifier circuit, comprising:

controlling the second bias current in accordance with one of first and second input voltages; and

controlling the first bias current using a predetermined constant current and a current substantially equal to the second bias current.

9. The method according to claim 8, wherein the step of controlling the first bias current includes producing the first bias current by adding the predetermined constant current to the current that is substantially equal to the second bias current.

10. The method according to claim 9, wherein the first and second bias currents change simultaneously.

11. The method according to claim 10, wherein the sum of the first and second bias currents is equal to the predetermined constant current.

12. An operational amplifier circuit comprising:

a first differential pair for receiving a first bias current and operating in response to first and second input voltages;

a second differential pair for receiving a second bias current and operating in response to the first and second input voltages;

a first current source connected to the first differential pair;

a second current source, which is connected to the second differential pair, for producing the second bias current; and

a control circuit, which is connected to the first and second current sources, for controlling the first current source such that the first current source produces a constant current, wherein the control circuit produces the first bias current at a node between the first differential pair and the first current source by adding a current that is substantially equal to the second bias current to the constant current in accordance with one of the first and second input voltages.

13. The operational amplifier circuit according to claim 12, wherein the control circuit includes:

a third current source connected to the second current source, wherein the third current source includes a first transistor for producing a current substantially equal to the second bias current; and

a second transistor, which is connected to the third current source and which has the same polarity as that of the first transistor, for controlling a current passing the first transistor in accordance with one of the first and second input voltages.

14. The operational amplifier circuit according to claim 12, wherein the control circuit includes:

a constant current source for producing a constant current that is a sum of the first and second bias currents;

a first transistor connected between the constant current source and a first power supply and connected to the first current source in a current mirror manner;

a second transistor connected between the constant current source and a second power supply and connected to the second current source in a current mirror manner;

a third transistor, which is connected to the second transistor in a current mirror manner, for producing a current substantially equal to the second bias current; and

a fourth transistor cascade-connected to the third transistor, wherein the drain of the fourth transistor is connected to the node between the first differential pair and the first current source, and the gate of the fourth transistor receives one of the first and second input voltages.

15. The operational amplifier circuit according to claim 12, further comprising:

a current mirror circuit connected to the first and second differential pairs; and

an output transistor, the gate of which is connected to the current mirror circuit, the drain of which is connected to a first power supply, and the source of which is connected to a second power supply.

16. An operational amplifier circuit comprising:

a first differential pair including a first P channel transistor responsive to a first input voltage and a second P channel transistor responsive to a second input voltage, wherein the first differential pair receives a first bias current;

a second differential pair including a first N channel transistor responsive to the first input voltage and a second N channel transistor responsive to the second input voltage, wherein the second differential pair receives a second bias current;

a first current source including a third P channel transistor connected between the first differential pair and a high-potential power supply;

a second current source, which includes a third N channel transistor connected between the second differential pair and a low-potential power supply, for producing the second bias current; and

a control circuit for controlling the first current source such that the first current source produces a predetermined constant current and for controlling the first and second bias currents, the control circuit including;

a third current source connected to the second current source, wherein the third current source includes a fourth N channel transistor that produces a current substantially equal to the second bias current; and

a fifth N channel transistor connected to the fourth N channel transistor and a node between the first current source and the first differential pair, wherein the fifth N channel transistor is responsive to one of the first and second input voltages.

17. The operational amplifier circuit according to claim 16, wherein at least a part of the first to fifth N channel transistors is replaced with an NPN bipolar transistor and at least a part of the first to third P channel transistors is replaced with a PNP bipolar transistor.

18. An operational amplifier circuit comprising:

a first differential pair including a first P channel transistor responsive to a first input voltage and a second P channel transistor responsive to a second input voltage, wherein the first differential pair receives a first bias current;

a second differential pair including a first N channel transistor responsive to the first input voltage and a second N channel transistor responsive to the second input voltage, wherein the second differential pair receives a second bias current;

a first current source including a third P channel transistor connected between the first differential pair and a high-potential power supply;

a second current source, which includes a third N channel transistor connected between the second differential pair and a low-potential power supply, for producing the second bias current; and

a control circuit for controlling the second current source such that the second current source produces a predetermined constant current and for controlling the first and second bias currents, the control circuit including;

a third current source connected to the first current source, wherein the third current source includes a fourth P channel transistor that produces a current substantially equal to the first bias current; and

a fifth P channel transistor connected to the fourth P channel transistor and a node between the second current source and the second differential pair, wherein the fifth P channel transistor is responsive to one of the first and second input voltages.

19. The operational amplifier circuit according to claim 18, wherein at least a part of the first to third N channel transistors is replaced with an NPN bipolar transistor, and at least a part of the first to fifth P channel transistors is replaced with a PNP bipolar transistor.

20. A control circuit, which is connected to a first power supply, for controlling a first output current flowing in a first current source including a first transistor cascade-connected to a second transistor that has the same polarity as that of the first transistor, the control circuit comprising:

a second current source connected to the first power supply, wherein the second current source includes a third transistor, and wherein a second output current that is substantially equal to the first output current flows to the second current source;

a fourth transistor cascade-connected to the third transistor, wherein the fourth transistor has the same polarity as that of the third transistor, and the second and fourth transistors control the first and second output currents by controlling saturation/non-saturation of the first and third transistors in accordance with a voltage signal; and

a third current source, which is connected to the second power supply, for producing a third output current, wherein a fourth output current, the phase of which is opposite to that of the first output current, is produced by adding the second output current and the third output current.

21. A semiconductor device including an operational amplifier circuit, wherein the operational amplifier circuit comprises:

a first differential pair for receiving a first bias current and operating in response to first and second input voltages;

a second differential pair for receiving a second bias current and operating in response to the first and second input voltages;

a first current source connected to the first differential pair;

a second current source, which is connected to the second differential pair, for producing the second bias current; and

a control circuit, which is connected to the first and second current sources, for controlling the first current source such that the first current source produces a constant current, wherein the control circuit produces the first bias current at a node between the first differential pair and the first current source-by adding a current substantially equal to the second bias current to the constant current in accordance with one of the first and second input voltages.

22. A semiconductor device including an operational amplifier circuit, wherein the operational amplifier comprises:

a first differential pair including a first P channel transistor responsive to a first input voltage and a second P channel transistor responsive to a second input voltage, wherein the first differential pair receives a first bias current;

a second differential pair including a first N channel transistor responsive to the first input voltage and a second N channel transistor responsive to the second input voltage, wherein the second differential pair receives a second bias current;

a first current source including a third P channel transistor connected between the first differential pair and a high-potential power supply;

a second current source, including a third N channel transistor connected between the second differential pair and a low-potential power supply, for producing the second bias current; and

a control circuit for controlling the first current source such that the first current source produces a predetermined constant current and for controlling the first and second bias currents, the control circuit including;

a third current source connected to the second current source, wherein the third current source includes a fourth N channel transistor that produces a current substantially equal to the second bias current; and

a fifth N channel transistor connected to the fourth N channel transistor and a node between the first current source and the first differential pair, wherein the fifth N channel transistor is responsive to one of the first and second input voltages.

23. A semiconductor device includes an operational amplifier circuit, wherein the operational amplifier circuit comprises:

a first differential pair including a first P channel transistor responsive to a first input voltage and a second P channel transistor responsive to a second input voltage, the first differential pair receiving a first bias current;

a second differential pair including a first N channel transistor responsive to the first input voltage and a second N channel transistor responsive to the second input voltage, the second differential pair receiving a second bias current;

a first current source including a third P channel transistor connected between the first differential pair and a high-potential power supply;

a second current source, including a third N channel transistor connected between the second differential pair and a low-potential power supply, for producing the second bias current; and

a control circuit for controlling the second current source such that the second current source produces a predetermined constant current and controlling the first and second bias currents, the control circuit including;

a third current source connected to the first current source and including a fourth P channel transistor that produces a current substantially equal to the first bias current; and

a fifth P channel transistor connected to the fourth P channel transistor and a node between the second current source and the second differential pair and responsive to one of the first and second input voltages.

24. An operational amplifier circuit comprising:

a constant current source circuit that includes a first transistor and a first resistor element connected between the gate and the source of the first transistor, wherein the constant current source circuit makes a first current flowing across the first resistor element equal to a first drain current flowing in the first transistor; and

an output stage circuit including first and second output transistors connected to an output terminal of the operational amplifier circuit, the second output transistor having the same polarity as that of the first transistor, the output stage circuit including a second resistor element connected between the source and the gate of the second output transistor, wherein the resistance of the second resistor element is proportional to the resistance of the first resistor element, and wherein a second current is produced from the first current in accordance with a current ratio expressed by a reciprocal of a ratio of the resistance of the first resistor element to the resistance of the second resistor element, and a gate voltage of the second output transistor is set by supplying the second current to the second resistor element.

25. The operational amplifier circuit according to claim 24, wherein the size of the second output transistor is proportional to the size of the first transistor, and a ratio of an idling current of the second output transistor to the first current coincides with a ratio of the size of the first transistor to the size of the second output transistor.

26. The operational amplifier circuit according to claim 25, wherein the ratio of the size of the first transistor to the size of the second output transistor is 1:

10.

27. The operational amplifier circuit according to claim 24, wherein the second current is produced by the output stage circuit and which is twice as large as the first current.

28. The operational amplifier circuit according to claim 24, wherein the constant current source circuit includes:

a second transistor, the source of which is connected to the first resistor element and the gate of which is connected to the drain of the first transistor; and

a current mirror circuit including a third transistor, the drain of which is connected to the drain of the first transistor, and a fourth transistor, the drain of which is connected to the drain of the third transistor.

29. The operational amplifier circuit according to claim 28, further comprising:

a differential input circuit including first and second input transistors for respectively receiving first and second input signals and a current mirror circuit that includes fifth and sixth transistors respectively connected to the first and second input transistors;

a seventh transistor connected to the third transistor in a current mirror manner;

an input stage circuit connected to the seventh transistor, wherein the input stage circuit includes a current source for supplying a bias current proportional to a drain current of the seventh transistor to the differential input circuit, and wherein the gate of the first output transistor is connected to a node between the sixth transistor and the second input transistor; and

an eighth transistor connected to the fifth transistor in a current mirror manner, wherein the drain of the eighth transistor is connected to the second resistor element, and wherein a ratio of the size of the eighth transistor to the size of the fifth transistor is a reciprocal of the ratio of the resistance of the first resistor element to the resistance of the second resistor element.

30. A current output circuit comprising:

a constant current source circuit that includes a first transistor and a first resistor element connected between the gate and the source of the first transistor, wherein the constant current source circuit makes a first current flowing across the first resistor element equal to a first drain current flowing in the first transistor; and

an output stage circuit including a second transistor and a second resistor element connected between the gate and the source of the second transistor, wherein the resistance of the second resistor element is proportional to the resistance of the first resistor element, and wherein the output stage circuit produces a second current from the first current in accordance with a current ratio expressed by a reciprocal of a ratio of the resistance of the first resistor element to the resistance of the second resistor element and sets a gate voltage of the second transistor by supplying, the second current to the second resistor element.

31. The current output circuit according to claim 30, wherein the size of the second transistor is proportional to the size of the first transistor, and a second drain current, which is set in accordance with a ratio of the size of the first transistor to the size of the second transistor with respect to the first current, flows in the second transistor.

32. The current output circuit according to claim 31, wherein the ratio of the size of the first transistor to the size of the second transistor is 1:

10.

33. The current output circuit according to claim 30, wherein the second current is produced by the output stage circuit produces and is twice as large as the first current.

34. The current output circuit according to claim 30, wherein the constant current source circuit includes:

a third transistor, the source of which is connected to the first resistor element and the gate of which is connected to the drain of the first transistor; and

a current mirror circuit including a fourth transistor, the drain of which is connected to the drain of the first transistor, and a fifth transistor, the drain of which is connected to the drain of the third transistor.

35. The current output circuit according to claim 34, wherein the output stage circuit includes a sixth transistor connected to the fourth transistor in a current mirror manner, the drain of the sixth transistor being connected to the second resistor element, wherein a ratio of the size of the fourth transistor to the size of the sixth transistor is a reciprocal of the ratio of the resistance of the first resistor element to the resistance of the second resistor element.

36. A semiconductor device including an operational amplifier circuit, wherein the operational amplifier circuit comprises:

a constant current source circuit that includes a first transistor and a first resistor element connected between the gate and the source of the first transistor, wherein the constant current source circuit makes a first current flowing across the first resistor element equal to a first drain current flowing in the first transistor; and

an output stage circuit including;

first and second output transistors connected to an output terminal of the operational amplifier circuit, the second output transistor having the same polarity as that of the first transistor; and

a second resistor element connected between the source and the gate of the second output transistor and having a resistance proportional to a resistance of the first resistor element, wherein a second current is produced from the first current in accordance with a current ratio expressed by a reciprocal of a ratio of the resistance of the first resistor element to the resistance of the second resistor element, and a gate voltage of the second output transistor is set by supplying the second current to the second resistor element.

37. A semiconductor device including a current output circuit, wherein the current output circuit comprises:

a constant current source circuit that includes a first transistor and a first resistor element connected between the gate and the source of the first transistor, wherein the constant current source circuit makes a first current flowing across the first resistor element equal to a first drain current flowing in the first transistor; and

an output stage circuit including a second transistor and a second resistor element connected between the gate and the source of the second transistor, wherein the resistance of the second resistor element is proportional to the resistance of the first resistor element, and wherein the output stage circuit produces a second current from the first current in accordance with a current ratio expressed by a reciprocal of a ratio of the resistance of the first resistor element to the resistance of the second resistor element and sets a gate voltage of the second transistor by supplying the second current to the second resistor element.

38. A current output circuit comprising:

a first transistor, the drain of which receives a first current;

a first resistor element connected between the gate and the source of the first transistor;

a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor, wherein a drain current is generated at the drain of the second transistor;

a second resistor element, the resistance of which is related to the resistance of the first resistor element; and

a third transistor, the size of which is related to the size of the first transistor, wherein the second resistor element is connected between the gate and the source of the third transistor, a second current originating from the drain current of the second transistor is supplied to the gate of the third transistor, and a third current, which is related to the first current, is produced at the drain of the third transistor.

39. The current output circuit according to claim 38, wherein the resistances of the first and second resistor elements and the second current are set such that a gate voltage of the first transistor becomes equal to a gate voltage of the third transistor, wherein a ratio of the first current to the third current is equal to a ratio of the size of the first transistor to the size of the third transistor.

40. The current output circuit according to claim 38, further comprising a current mirror circuit, which is connected to the drains of the second and third transistors, for receiving the drain current of the second transistor and producing the second current.

41. The current output circuit according to claim 40, wherein the current mirror circuit includes an input transistor connected to the second transistor and an output transistor connected to the third transistor, wherein a ratio of the size of the input transistor to the size of the output transistor is set to a reciprocal of the ratio of the resistance of the first resistor element to the resistance of the second resistor element.

42. An analog switch circuit comprising:

a first transistor, the drain of which receives a first current;

a first resistor element connected between the gate and the source of the first transistor;

a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor, wherein a drain current is generated at the drain of the second transistor;

a differential pair including an input transistor, the source of which receives a second current originating from the drain current of the second transistor and the gate of which receives an input signal, wherein the differential pair includes an output transistor, the source of which receives the second current, the gate of which is connected to an output terminal of the analog switch circuit, and the drain of which is connected to the gate of the output transistor;

a second resistor element connected to the drain of the input transistor, wherein the resistance of the second resistor element is related to the resistance of the first resistor element; and

a third transistor, the size of which is related to the size of the first transistor, wherein the second resistor element is connected between the gate and the source of the third transistor, the drain of the third transistor is connected to the drain of the output transistor, and a third current, which is related to the first current, is generated at the drain of the third transistor.

43. The analog switch circuit according to claim 42, wherein the resistances of the first and second resistor elements and the second current are set such that a gate voltage of the first transistor becomes equal to a gate voltage of the third transistor.

44. The analog switch circuit according to claim 43, further comprising a current mirror circuit for producing the second current by mirroring the drain current of the second transistor.

45. The analog switch circuit according to claim 44, wherein the current mirror circuit includes a first current mirror transistor connected to the second transistor and a second current mirror transistor connected to the input and output transistors, and a ratio of the size of the first current mirror transistor to a size of the second current mirror transistor is equal to a ratio of the drain current of the second transistor to the total current flowing in the input and output transistors.

46. An operational amplifier circuit comprising:

a first transistor the drain of which receives a first current;

a first resistor element connected between the gate and the source of the first transistor;

a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor;

a differential pair including first and second differential transistors, the sources of which receive a second current originating from the drain current of the second transistor and the gates of which respectively receive first and second input signals;

second and third resistor elements respectively connected to the drains of the first and second differential transistors;

a third transistor, the gate of which is connected to a first node between a first terminal of the second resistor element and the drain of the first differential transistor, wherein the source of the third transistor is connected to a second terminal of the second resistor element, and a third current, which is related to the first current, is generated at the drain of the third transistor;

a first output transistor, the gate of which is connected to a second node between a third terminal of the third resistor element and the drain of the second differential transistor, wherein the source of the first output transistor is connected to a fourth terminal of the third resistor element, and a fourth current, which is related to the first current, is generated at the drain of the first output transistor;

a fourth resistor element connected to the drain of the third transistor; and

a second output transistor, the gate of which is connected to a third node between the drain of the third transistor and the fourth resistor element, wherein the source of the second output transistor is connected to the fourth resistor element, and a fifth current, which corresponds to a gate voltage of the third transistor, is generated at the drain of the second output transistor based on the third current.

47. The operational amplifier circuit according to claim 46, wherein the resistances of the first to third resistor elements and the second current are set such that a gate voltage of the first transistor becomes substantially equal to gate voltages of the third transistor and the first output transistor.

48. The operational amplifier circuit according to claim 47, further comprising a current mirror circuit for producing the second current by mirroring the drain current of the second transistor.

49. The operational amplifier circuit according to claim 48, wherein the current mirror circuit includes a first current mirror transistor connected to the second transistor and a second current mirror transistor connected to the sources of the first and second differential transistors, and a ratio of the size of the first current mirror transistor to the size of the second current mirror transistor is equal to a ratio of the drain current of the second transistor to the total current flowing in the first and second differential transistors.

50. The operational amplifier circuit according to claim 46, further comprising:

a constant current source circuit which includes a fourth transistor and a fifth resistor element connected between the gate and the source of the fourth transistor, wherein the constant current source controls a gate voltage of the fourth transistor such that a sixth current flowing across the fifth resistor element coincides with a drain current of the fourth transistor, wherein the constant current source produces the first current, and the first current is substantially equal to the drain current of the fourth transistor, and wherein a ratio of the sixth current to the third current is set to a reciprocal of a ratio of the resistance of the fourth resistor element to the resistance of the fifth resistor element, and a gate voltage of the second output transistor is determined by the resistance of the fourth resistor element and the third current.

51. The operational amplifier circuit according to claim 50, wherein the size of the second output transistor is proportional to the size of the fourth transistor and a ratio of the fifth current to the sixth current coincides with a ratio of the size of the fourth transistor to the size of the second output transistor.

52. The operational amplifier circuit according to claim 50, wherein the constant current source circuit includes:

a fifth transistor, the source of which is connected to the fifth resistor element and the gate of which is connected to the drain of the fourth transistor; and

a second current mirror circuit including a first current mirror transistor connected to the drain of the fourth transistor and a second current mirror transistor connected to the drain of the fifth transistor.

53. A semiconductor device including a current output circuit, wherein the current output circuit comprises:

a first transistor, the drain of which receives a first current;

a first resistor element connected between the gate and the source of the first transistor;

a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor, wherein a drain current is generated at the drain of second transistor;

a second resistor element the resistance of which is related to the resistance of the first resistor element; and

a third transistor the size of which is related to the size of the first transistor, wherein the second resistor element is connected between the gate and the source of the third transistor, a second current originating from the drain current of the second transistor is supplied to the gate of the third transistor, and a third current, which is related to the first current, is generated at the drain of the third transistor.

54. A semiconductor device including an analog switch circuit, wherein the analog switch circuit comprises:

a first transistor, the drain of which receives a first current;

a first resistor element connected between the gate and the source of the first transistor;

a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor, wherein a drain current is generated at the drain of the second transistor;

a differential pair including an input transistor and an output transistor, wherein the source of the input transistor receives a second current originating from the drain current of the second transistor and the gate of the input transistor receives an input signal, and the source of the output transistor receives the second current, the gate of the output transistor is connected to an output terminal of the analog switch circuit, and the drain the output transistor is connected to the gate of the output transistor;

a second resistor element connected to the drain of the input transistor, wherein the resistance of the second resistor is related to the resistance of the first resistor element; and

a third transistor, the size of which is related to the size of the first transistor, wherein the second resistor element is connected between the gate and the source of the third transistor whose drain is connected to the drain of the output transistor, and a third current, which is related to the first current, is generated at the drain of the third transistor.

55. A semiconductor device including an operational amplifier circuit, wherein the operational amplifier circuit comprises:

a first transistor, the drain of which receives a first current;

a first resistor element connected between the gate and the source of the first transistor;

a second transistor, the gate of which is connected to the drain of the first transistor and the source of which is connected to the gate of the first transistor;

a differential pair including first and second differential transistors, the sources of which receive a second current originating from the drain current of the second transistor and the gates of which respectively receive first and second input signals;

second and third resistor elements respectively connected to the drains of the first and second differential transistors;

a third transistor, the gate of which is connected to a first node between a first terminal of the second resistor element and the drain of the first differential transistor, and the source of which is connected to a second terminal of the second resistor element, wherein a third current, which is related to the first current, is generated at the drain of the third transistor;

a first output transistor, the gate of which is connected to a second node between a third terminal of the third resistor element and the drain of the second differential transistor, and the source of which is connected to a fourth terminal of the third resistor element, wherein a fourth current, which is related to the first current, is generated at the drain of the first output transistor;

a fourth resistor element connected to the drain of the third transistor; and

a second output transistor, the gate of which is connected to a third node between the drain of the third transistor and the fourth resistor element, and the source of which is connected to the fourth resistor element, wherein a fifth current, which corresponds to a gate voltage of the third transistor, is generated at the drain of second output transistor the based on the third current.