High voltage row and column driver for programmable resistance memory

• US 20030206428A1
• Filed: 05/01/2002
• Published: 11/06/2003
• Est. Priority Date: 05/01/2002
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC (Micron Technology, Inc.)
• Original Assignee: Ovonyx Incorporated (Micron Technology, Inc.)
• Inventors: Parkinson, Ward
• Granted Patent: US 6,781,860 B2
• Time in Patent Office: Days
• US Class Current: 365/100
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A driver circuit having one or more MOS transistors. The driver circuit is capable of providing an output voltage greater than the power supply voltage; however, the magnitude of the voltages appearing across the terminals of the MOS transistors are preferably less than or equal to the magnitude of the power supply voltage. The driver circuit may comprise a plurality of serially coupled PMOS transistors and a plurality of serially coupled NMOS transistors wherein the plurality of PMOS transistors and plurality of NMOS transistors are coupled at the output node of the driver.

Claims

1. A memory system, comprising:

a programmable resistance memory cell coupled to a column line and a row line; and

a driver circuit having an output node for outputting an output voltage to the column line and/or the row line, the driver circuit comprising;

a plurality of PMOS transistors coupled in series between said output node and a first node of said driver circuit,

a plurality of NMOS transistors coupled is series between said output node and a second node of said driver circuit.

2. The memory system of claim 1, further comprising a control circuit including a first additional PMOS transistor coupled in series with a second additional PMOS transistor, said control circuit outputting a control voltage to a gate at least one of said plurality of PMOS transistors.

3. The memory system of claim 1, wherein said first additional PMOS transistor is coupled to said second additional PMOS transistor at a connection point, said connection point coupled to said gate, said control voltage outputted from said connection point.

4. The memory system of claim 1, wherein said first node is supplied with a first voltage and said second node is supplied with a ground voltage.

5. The memory system of claim 4, further comprising a switching circuit selectively coupling a second voltage to said output node.

6. The memory system of claim 5, wherein said first voltage is greater than said power supply voltage.

7. The memory system of claim 5, further comprising a logic circuit having a first logic effective to couple said first voltage to said output node, a second logic effective to coupled 1 said second voltage to said output node, and a third logic effective to couple said ground voltage to said output node.

8. The memory system of claim 4, wherein said plurality of PMOS transistors includes a first and a second PMOS transistor, said plurality of NMOS transistors includes a first and a second NMOS transistor, a source of said first PMOS transistor being coupled to said first node, a drain of said first PMOS transistor being coupled to a source of said second PMOS transistor, a drain of said second PMOS transistor being coupled to a drain of said first NMOS transistor at said output node, a source of first NMOS transistor being coupled to a drain of said second NMOS transistor, a source of said second NMOS transistor being coupled to said second node.

9. The memory system of claim 8, wherein a gate of said second PMOS transistor and a gate of said first NMOS transistor are coupled to a second voltage.

10. The memory system of claim 9, further comprising a third PMOS transistor and a fourth PMOS transistor coupled in series at a connection point, said connection point coupled to a gate of said first PMOS transistor.

11. The memory system of claim 10, wherein a gate of said third PMOS transistor and a gate of said fourth PMOS transistor are coupled to said second voltage.

12. The memory system of claim 9, wherein said second voltage is a power supply voltage.

13. The memory system of claim 12, wherein said first voltage is greater than said power supply voltage.

14. The memory system of claim 13, wherein said first voltage is less than or equal to said power supply voltage multiplied by two.

15. The memory system of claim 9, further comprising a switching circuit selectively coupling said second voltage to said output node.

16. The memory system of claim 15, wherein said switching circuit comprises a fifth PMOS transistor coupled in series with a third NMOS transistor.

17. The memory system of claim 16, wherein a source of said fifth PMOS transistor is coupled to said first node, a drain of said fifth PMOS transistor is coupled to a drain of said third NMOS transistor, a source of said third NMOS transistor is coupled to said output node.

18. The memory system of claim 7, wherein an output from a row and/or column decoder circuit is an input to said logic circuit.

19. The memory system of claim 1, wherein the programmable resistance memory cell comprises a phase change material.

20. A memory system, comprising:

a programmable resistance memory cell coupled to a column line and a row line; and

a driver circuit having an output node for outputting an output voltage to the column line and/or the row line, the driver circuit comprising;

a plurality of PMOS transistors coupled in series,

a plurality of NMOS transistors coupled is series,

said plurality of PMOS transistors being coupled in series with said plurality of NMOS at said output node.

21. The memory system of claim 20, further comprising a control circuit including a first additional PMOS transistor coupled in series with a second additional PMOS transistor, said control circuit outputting a control voltage to a gate at least one of said plurality of PMOS transistors.

22. The memory system of claim 20, wherein said first additional PMOS transistor is coupled to said second additional PMOS transistor at a connection point, said connection point coupled to said gate, said control voltage outputted from said connection point.

23. The memory system of claim 20, wherein said plurality of PMOS transistors is coupled between a first node supplied with a first voltage and said second node is supplied with a ground voltage.

24. The memory system of claim 23, further comprising a switching circuit selectively coupling a second voltage to said output node.

25. The memory system of claim 24, wherein said second voltage is a power supply voltage, said first voltage being greater than said power supply voltage.

26. The memory system of claim 24, wherein said further comprising a logic circuit having a first logic effective to couple said first voltage to said output node, a second logic effective to coupled said second voltage to said output node, and a third logic effective to couple said ground voltage to said output node.

27. The memory system of claim 24, wherein said plurality of PMOS transistors includes a first and a second PMOS transistor, said plurality of NMOS transistors includes a first and a second NMOS transistor, a source of said first PMOS transistor being coupled to said first node, a drain of said first PMOS transistor being coupled to a source of said second PMOS transistor, a drain of said second PMOS transistor being coupled to a drain of said first NMOS transistor at said output node, a source of first NMOS transistor being coupled to a drain of said second NMOS transistor, a source of said second NMOS transistor being coupled to said second node.

28. The memory system of claim 27, wherein a gate of said second PMOS transistor and a gate of said first NMOS transistor are coupled to a second voltage.

29. The memory system of claim 28, further comprising a third PMOS transistor and a fourth PMOS transistor coupled in series at a connection point, said connection point coupled to a gate of said first PMOS transistor.

30. The memory system of claim 29, wherein a gate of said third PMOS transistor and a gate of said fourth PMOS transistor are coupled to said second voltage.

31. The memory system of claim 28, wherein said second voltage is a power supply voltage.

32. The memory system of claim 31, wherein said first voltage is greater than said power supply voltage.

33. The memory system of claim 32, wherein said first voltage is less than or equal to said power supply voltage multiplied by two.

34. The memory system of claim 28, further comprising a switching circuit selectively coupling said second voltage to said output node.

35. The memory system of claim 34, wherein said switching circuit comprises a fifth PMOS transistor coupled in series with a third NMOS transistor.

36. The memory system of claim 35, wherein a source of said fifth PMOS transistor is coupled to said first node, a drain of said fifth PMOS transistor is coupled to a drain of said third NMOS transistor, a source of said third NMOS transistor is coupled to said output node.

37. The memory system of claim 26, wherein an output from a row and/or column decoder circuit is an input to said logic circuit.

38. The memory system of claim 20, wherein the programmable resistance memory cell comprises a phase change material.

39. A memory system, comprising:

a programmable resistance memory cell coupled to a column line and a row line; and

a driver circuit having at least one MOS transistor, said driver circuit outputting an output voltage from an output node to the column line and/or the row line, the driver circuit having a first node supplied with a first voltage and a second node supplied with a second voltage, the magnitude of said first voltage being greater than the magnitude of said second voltage, said driver circuit adapted so that said output voltage is capable of having a magnitude greater than the magnitude of said second voltage, said driver circuit further adapted so that voltages across a drain and a source of said MOS transistor, a gate and the drain of said MOS transistor, and the gate and the source of said MOS transistors have magnitudes that are less than or equal to the magnitude of said second voltage.

40. The memory system of claim 39, wherein the magnitude of said output voltage is less than or equal to the magnitude of said first voltage.

41. The memory system of claim 39, wherein the magnitude of said first voltage is twice the magnitude of said second voltage.

42. The memory system of claim 39, wherein said second voltage is power supply voltage.

43. The memory system of claim 39, wherein said at least one MOS transistor comprises:

at least a first and a second PMOS transistor coupled in series between a first node supplied with said first voltage and said output node, and

at least a first and a second NMOS transistor coupled in series between said output node and a second node supplied with a third voltage.

44. The memory system of claim 43, wherein a source of said first PMOS transistor being coupled to said first node, a drain of said first PMOS transistor being coupled to a source of said second PMOS transistor, a drain of said second PMOS transistor being coupled to a drain of said first NMOS transistor at said output node, a source of first NMOS transistor being coupled to a drain of said second NMOS transistor, a source of said second NMOS transistor being coupled to said second node.

45. The memory system of claim 44, wherein a gate of said second PMOS transistor and a gate of said first NMOS transistor are commonly coupled to said second voltage.

46. The memory system of claim 44, further comprising a third PMOS transistor and a fourth PMOS transistor coupled in series at a connection point, said connection point coupled to a gate of said first PMOS transistor.

47. The memory system of claim 43, wherein said third voltage is a ground voltage.

48. The memory system of claim 39, wherein said programmable resistance memory cell comprises a phase change material.

49. A driver circuit, comprising:

at least one MOS transistor, said driver circuit outputting an output voltage from an output node, the driver circuit having a first node supplied with a first voltage and a second node supplied with a second voltage, the magnitude of said first voltage being greater than the magnitude of said second voltage, said driver circuit adapted so that said output voltage is capable of having a magnitude greater than the magnitude of said second voltage, said driver circuit further adapted so that voltages across a drain and a source of said MOS transistor, a gate and the drain of said MOS transistor, and the gate and the source of said MOS transistors have magnitudes that are less than or equal to the magnitude of said second voltage.

50. The driver circuit of claim 49, wherein the magnitude of said output voltage is less than or equal to the magnitude of said first voltage.

51. The driver circuit of claim 49, wherein the magnitude of said first voltage is twice the magnitude of said second voltage.

52. The driver circuit of claim 49, wherein said second voltage is power supply voltage.

53. The driver circuit of claim 49, wherein said at least one MOS transistor comprises:

at least a first and a second PMOS transistor coupled in series between a first node supplied with said first voltage and said output node, and

at least a first and a second NMOS transistor coupled in series between said output node and a second node supplied with a third voltage.

54. The driver circuit of claim 53, wherein a source of said first PMOS transistor being coupled to said first node, a drain of said first PMOS transistor being coupled to a source of said second PMOS transistor, a drain of said second PMOS transistor being coupled to a drain of said first NMOS transistor at said output node, a source of first NMOS transistor being coupled to a drain of said second NMOS transistor, a source of said second NMOS transistor being coupled to said second node.

55. The driver circuit of claim 54, wherein a gate of said second PMOS transistor and a gate of said first NMOS transistor are commonly coupled to said second voltage.

56. The driver circuit of claim 54, further comprising a third PMOS transistor and a fourth PMOS transistor coupled in series at a connection point, said connection point coupled to a gate of said first PMOS transistor.

57. The driver circuit of claim 53, wherein said third voltage is a ground voltage.