Nonvolatile semiconductor memory device

• US 20030206438A1
• Filed: 05/22/2003
• Published: 11/06/2003
• Est. Priority Date: 09/28/2000
• Status: Active Grant

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Tomoharu, Shibata, Noboru
• Granted Patent: US 6,937,512 B2
• Time in Patent Office: Days
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements

Abstract

A memory cell array has a first and a second storage area. The first storage area has a plurality of memory elements selected by an address signal. The second storage area has a plurality of memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Claims

1. A semiconductor memory device comprising:

a memory cell array with a first and a second storage area, said first storage area having a plurality of memory elements selected by an address signal and said second storage area having a plurality of memory elements selected by a control signal; and

a control circuit which has a fuse element and, when said fuse element has been blown, inhibits at least one of writing and erasing from being done on said second storage area.