Anti-fuse structure and method of writing and reading in integrated circuits

• US 20030207526A1
• Filed: 06/05/2003
• Published: 11/06/2003
• Est. Priority Date: 06/02/2001
• Status: Active Grant

• Current Assignee: Kemal Tamer San, Tito Gelsomini
• Original Assignee: Kemal Tamer San, Tito Gelsomini
• Inventors: Gelsomini, Tito, San, Kemal Tamer
• Granted Patent: US 6,781,887 B2
• Time in Patent Office: Days
• US Class Current: 438/200
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

Claims

1. An integrated circuit chip comprising:

an integrated circuit (IC) in a semiconductor subs-rate;

an information write-register circuit embedded in said IC, said write-register having a plurality of independently addressable components;

each of said components formed as an isolated p-well nested in an isolated n-well, said p-well having a gate for control; and

said gate positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into said component.

2. The integrated circuit according to claim 1 further including means for applying an overstress voltage pulse between said gate and said isolated p-well, created when a write-mode pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

3. The integrated circuit according to claim 1 further including a gate-controlled component formed as said isolated p-well nested in an isolated n-well, said p-well having two electrical terminals, and a control gate separated from said isolated p-well by said insulator.

4. The integrated circuit according to claim 3 wherein said device is structurally a MOS transistor and said gate is made of poly-silicon or another conductive material.

5. The integrated circuit according to claim 1 wherein said gate insulator is made of a material selected from a group consisting of silicon dioxide, perovskite or other insulating material in the thickness range from about 2 to 10 nm.

6. The silicon circuit according to claim 2 wherein said means is capable of generating an overstress voltage pulse in the range from about 8 to 10 V, composed of said write-enable pulse ranging from about +4 to +5 V and about 10 to 50 μ

s duration, and said p-well pulse ranging from about −

4 to −

5 V and about 7 to 40 μ

s duration.

7. The integrated circuit according to claim 1 wherein said binary encoded information includes data about identification, fabrication, characterization, design and performance of said integrated circuit, or any other data concerning device performance, history, ownership, or encoded signatures.

8. The integrated circuit according to claim 1 further having transistors arranged in an information read-register circuit operable to read data encoded in said write-register.

9. A method of fabricating an information write-register circuit, comprising the steps of:

forming an integrated circuit in a semiconductor substrate;

forming a write-register in said substrate, comprising a plurality of independently addressable gate-controlled components in isolated p-wells nested in isolated n-wells;

forming said components with an insulator having a geometry locally susceptible to electrical conductivity upon applying an overstress voltage pulse; and

forming said gates onto said insulator to accept said overstress pulses between said gate and said isolated p-well.

10. The method according to claim 9 wherein said forming of a write-register is performed concurrently with said forming of an integrated circuit.

11. The method according to claim 9 further comprising the step of concurrently forming in said circuit means for reading data encoded in said write-register.

12. A method or encoding data into the write-register of an integrated circuit having a plurality of components including a gate-controlled insulator over an isolated p-well, comprising the steps of:

applying an overstress voltage pulse between said component gate and said isolated p-well, thereby locally inverting the insulating character of said gate insulator, to permanently encode binary data into said write-register; and

controlling said pulses by superposing a write-enable pulse of predetermined polarity and duration with a p-well pulse of opposite polarity and shorter duration.

13. The method according to claim 12 wherein the step of controlling said pulses by superposing said write-enable pulse and said p-well pulse includes the steps of:

loading the data, to be encoded in said write-register, into the shift register associated with said write-register;

initiating the write-enable voltage pulse by increasing the power supply voltage to a predetermined value;

after a time delay of about 1 μ

s, initiating directly from the user said p-well voltage pulse, said p-well pulse having a polarity opposite to the polarity of said write-enable voltage pulse and a magnitude such that the absolute voltage sum of said p-well pulse and said write-enable pulse is sufficient to locally invert the insulating character of said gate insulator;

after a time duration sufficient to locally invert said insulating character to electrical conductivity, discontinuing said p-well pulse; and

after a delay of about 1 μ

s, discontinuing said write-enable pulse.

14. The method according to claim 12 wherein locally inverting said gate insulator by an overstress voltage pulse encodes the first binary digit as a “

logic 0”

in said component.

15. The method according to claim 12 wherein preserving said insulating character of said gate insulator encodes the second binary digit as a “

logic 1”

in said component.

16. The method according to claim 12 wherein said overstress pulses are applied while said integrated circuit is still portion of a semiconductor wafer.

17. The method according to claim 12 wherein said overstress pulses are also applied after said integrated circuit has been singulated from said wafer, assembled and packaged.