Anti-fuse structure and method of writing and reading in integrated circuits
First Claim
1. An integrated circuit chip comprising:
- an integrated circuit (IC) in a semiconductor subs-rate;
an information write-register circuit embedded in said IC, said write-register having a plurality of independently addressable components;
each of said components formed as an isolated p-well nested in an isolated n-well, said p-well having a gate for control; and
said gate positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into said component.
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Abstract
An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.
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Citations
17 Claims
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1. An integrated circuit chip comprising:
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an integrated circuit (IC) in a semiconductor subs-rate;
an information write-register circuit embedded in said IC, said write-register having a plurality of independently addressable components;
each of said components formed as an isolated p-well nested in an isolated n-well, said p-well having a gate for control; and
said gate positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into said component. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of fabricating an information write-register circuit, comprising the steps of:
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forming an integrated circuit in a semiconductor substrate;
forming a write-register in said substrate, comprising a plurality of independently addressable gate-controlled components in isolated p-wells nested in isolated n-wells;
forming said components with an insulator having a geometry locally susceptible to electrical conductivity upon applying an overstress voltage pulse; and
forming said gates onto said insulator to accept said overstress pulses between said gate and said isolated p-well. - View Dependent Claims (10, 11)
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12. A method or encoding data into the write-register of an integrated circuit having a plurality of components including a gate-controlled insulator over an isolated p-well, comprising the steps of:
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applying an overstress voltage pulse between said component gate and said isolated p-well, thereby locally inverting the insulating character of said gate insulator, to permanently encode binary data into said write-register; and
controlling said pulses by superposing a write-enable pulse of predetermined polarity and duration with a p-well pulse of opposite polarity and shorter duration. - View Dependent Claims (13, 14, 15, 16, 17)
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Specification