Structure and method of MOS transistor having increased substrate resistance

• US 20030207543A1
• Filed: 05/28/2003
• Published: 11/06/2003
• Est. Priority Date: 01/14/2002
• Status: Active Grant

• Current Assignee: Che-Jen Hu, Craig T. Salling, Zhiqiang Wu
• Original Assignee: Che-Jen Hu, Craig T. Salling, Zhiqiang Wu
• Inventors: Wu, Zhiqiang, Hu, Che-Jen, Salling, Craig T.
• Granted Patent: US 6,764,909 B2
• Time in Patent Office: Days
• US Class Current: 438/309
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 27/0277 involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
• CPC Class Codes: H01L 29/1079 with insulated gate

Abstract

Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.

Claims

1. An integrated circuit fabricated in a semiconductor of a first conductivity type, said circuit having at the surface at least one lateral MOS transistor comprising:

a source and a drain, each having at said surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and

a semiconductor region within said semiconductor of said first conductivity type, having a resistivity higher than the remainder of said semiconductor, said region extending vertically below said transistor while laterally limited to the area of the transistor such that the resistivity under said gate is different from the resistivity under said source and drain regions.

2. The circuit according to claim 1 wherein said semiconductor of the first conductivity type is a semiconductor epitaxial layer.

3. The circuit according to claim 1 wherein said semiconductor material is selected from a group consisting of silicon, silicon germanium, gallium arsenide, and any other semiconductor material used in integrated circuit fabrication.

4. The circuit according to claim 1 wherein said region of higher resistivity within said semiconductor of the first conductivity type has a resistivity at least an order of magnitude higher than the resistivity of said semiconductor of the first conductivity type.

5. The circuit according to claim 1 wherein said semiconductor of the first conductivity type is made of p-type silicon in the resistivity range from about 1 to 50 Ω

cm, and said source, drain, and their extensions are made of n-type silicon.

6. The circuit according to claim 1 wherein said semiconductor of the first conductivity type has a dopant species selected from a group consisting of boron, aluminum, gallium, and indium, while said source, drain, their extensions, and said region of higher resistivity within said semiconductor of the first conductivity type have a dopant species selected from a group consisting of arsenic, phosphorus, antimony, and bismuth.

7. The circuit according to claim 1 wherein said semiconductor of the first conductivity type is made of n-type silicon in the resistivity range from about 5 to 50 Ω

cm, and said source, drain, and their extensions are made of p-type silicon.

8. The circuit according to claim 1 wherein said semiconductor of the first conductivity type has a dopant species selected from a group consisting of arsenic, phosphorus, antimony, bismuth, and lithium, while said source, drain, their extensions, and said region of higher resistivity within said semiconductor of the first conductivity type have a dopant species selected from a group consisting of boron, aluminum, gallium, indium, and lithium.

9. The circuit according to claim 1 wherein said gate has a narrow dimension from about 0.2 to 1.0 μ

m.

10. The circuit according to claim 1 wherein said region of higher resistivity is the substrate of said transistor, enabling full functioning of said transistor while not affecting operation of neighboring active devices.

11. The circuit according to claim 10 wherein said region of higher resistivity further improves the ESD protection of said transistor without decreasing latch-up robustness or increasing inadvertent substrate current-induced body biasing of neighboring transistors.

12. An integrated circuit fabricated in a semiconductor of a first conductivity type, said circuit having at the surface at least one lateral MOS transistor comprising:

a source and a drain, each having at said surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and

a semiconductor region within said semiconductor of said first conductivity type, having a resistivity higher than the remainder of said semiconductor, said region extending vertically below said transistor while laterally limited to the area of the transistor, and embedded in said region a volume of said opposite conductivity type, said volume thereby further impeding the flow of substrate current from said transistor.

13. The circuit according to claim 12 wherein said semiconductor of the first conductivity type is a semiconductor epitaxial layer.

14. A method of increasing the p-type semiconductor resistivity under the active area of a high-voltage NMOS transistor having a gate, comprising the steps of:

depositing a photoresist layer over said transistor and opening a window in said layer over said active area of said transistor; and

implanting, at high energy, n-doping ions into said p-type semiconductor through said window, creating a deep region having a net p-type doping lower than that of said p-type semiconductor remote from said transistor active area.

15. A method of fabricating an NMOS transistor in the surface of an integrated circuit, said transistor having increased substrate resistance in the p-type semiconductor of said integrated circuit, comprising the steps of:

forming non-conductive electrical isolation regions into said p-type semiconductor for defining the lateral boundaries of the NMOS transistor active area;

implanting p-doping or n-doping ions to adjust the background doping level of said p-type semiconductor;

depositing over said surface a layer of insulating material suitable as gate dielectric, covering said transistor area;

depositing a layer of poly-silicon or other conductive material onto said insulating layer;

protecting a portion of said poly-silicon and etching the remainder thereof, defining the gate area of said transistor;

depositing a first photoresist layer and opening a window therein, exposing the surface of said area between said isolation regions;

implanting, at low energy, n-doping ions into said exposed surface area, creating shallow n-doped layers under said surface, suitable as extended source and drain of said transistor;

implanting, at high energy, n-doping ions into said exposed surface area, creating a deep region under said surface having a net p-type doping lower than that of said p-type semiconductor remote from said transistor active area;

removing said first photoresist layer;

depositing conformal insulating layers of an insulator, such as silicon nitride or silicon dioxide, over said surface and directional plasma etching said insulating layers so that only side walls around the poly-silicon gate remain;

depositing a second photoresist layer and opening a window therein, exposing the surface of said area between said isolation regions;

implanting, at medium energy, n-doping ions into said exposed surface area, creating an n-doped region that extends to a medium depth under said surface, suitable as deep source and drain of said transistor; and

removing said second photoresist layer.

16. The method according to claim 15 wherein the thickness of said first photoresist layer is larger than a thickness solely required to block said low-energy ion implant.

17. The method according to claim 15 further comprising the step of annealing said high energy implant at elevated temperature.

18. The method according to claim 15 comprising the modified process step of implanting said n-doping ions at high energy after said process step of implanting said n-doping ions at medium energy.

19. The method according to claim 15 wherein said p-type semiconductor has a peak doping concentration between 4·

10E17 and 1·

10E18 cm-3 after said background doping adjustment implant.

20. The method according to claim 15 wherein said implanting of low energy ions comprises ions having an energy suitable for creating the junction at a depth between 10 and 50 nm, and a peak concentration from about 5·

10E17 to 5·

10E20 cm-3.

21. The method according to claim 15 wherein said implanting of medium energy ions comprises ions having an energy suitable for creating the junction at a depth between 50 and 200 nm, and a peak concentration from about 5·

10E19 to 5·

10E20 cm-3.

22. The method according to claim 15 wherein said implanting of high energy ions comprises ions having an energy range from about 400 to 550 keV and a dose of about 5·

10E12 to 2·

10E13 cm-2 to achieve a concentration from about 1·

10E17 to 6·

10E17 cm-3 at a depth of more than 200 nm.

23. The method according to claim 15 wherein said implanting of high energy ions comprises ions selected in the energy range from about 400 to 700 keV such that the peak concentration is at a different depth than that of the p-type semiconductor, and in the dose range of about 8·

E112 to 8·

10E13 cm-2 to overcompensate the p-type semiconductor doping and to create a region of the opposite conductivity type.

24. The method according to claim 15 wherein said net p-type doping of low concentration comprises a peak concentration of about 1 to 6 E17 cm-3 below the p-n junctions of said transistor'"'"'s deep source and drain regions.

25. A method of increasing the n-type semiconductor resistivity under the active area of a high-voltage PMOS transistor having a gate, comprising the steps of:

depositing a photoresist layer over said transistor and opening a window in said layer over said active area of said transistor; and

implanting, at high energy, p-doping ions into said n-type semiconductor through said window, creating a deep region having a net n-type doping lower than that of said n-type semiconductor remote from said transistor active area.

26. A method of fabricating a PMOS transistor in the surface of an integrated circuit, said transistor having increased substrate resistance in the n-type semiconductor of an integrated circuit, comprising the steps of:

forming non-conductive electrical isolation regions into said n-type semiconductor for defining the lateral boundaries of the PMOS transistor active area;

implanting n-doping or p-doping ions to adjust the background doping level of said n-type semiconductor;

depositing over said surface a layer of insulating material suitable as gate dielectric, covering said transistor area;

depositing a layer of poly-silicon or other conductive material onto said insulating layer;

protecting a portion of said poly-silicon and etching the remainder thereof, defining the gate area of said transistor;

depositing a first photoresist layer and opening a window therein, exposing the surface of said area between said isolation regions;

implanting, at low energy, p-doping ions into said exposed surface area, creating shallow p-doped layers under said surface, suitable as extended source and drain of said transistor;

implanting, at high energy, p-doping ions into said exposed surface area, creating a deep region under said surface having a net n-type doping lower than that of said n-type semiconductor remote from said transistor active area;

removing said first photoresist layer;

depositing conformal insulating layers of an insulator, such as silicon nitride or silicon dioxide, over said surface and directional plasma etching said insulating layers so that only side walls around the poly-silicon gate remain;

depositing a second photoresist layer and opening a window therein, exposing the surface of said area between said insulation regions;

implanting, at medium energy, p-doping ions into said exposed surface area, creating an p-doped region that extends to a medium depth under said surface, suitable as deep source and drain of said transistor; and

removing said second photoresist layer.

27. The method according to claim 26 comprising the modified process step of implanting said p-doping ions at high energy after said process step of implanting said p-doping ions at medium energy.

28. The method according to claim 26 wherein said n-type semiconductor has a peak doping concentration between 4·

10E17 and 1·

10E18 cm-3 after said background doping adjustment implant.

29. The method according to claim 26 wherein said implanting of low energy ions comprises ions having an energy suitable for creating the junction at a depth between 10 and 50 nm, and a peak concentration from about 5·

10E17 to 5·

10E20 cm-3.

30. The method according to claim 26 wherein said implanting of medium energy ions comprises ions having an energy suitable for creating the junction at a depth between 50 and 200 nm, and a peak concentration from about 5·

10E19 to 5·

10E20 cm-3.

31. The method according to claim 26 wherein said implanting of high energy ions comprises ions having an energy range from about 400 to 550 keV and a dose of about 5·

10E12 to 2·

10E13 cm-2 to achieve a concentration from about 1·

10E17 to 6·

10E17 cm-3 at a depth of more than 200 nm.

32. The method according to claim 26 wherein said implanting of high energy ions comprises ions selected in the energy range from about 400 to 700 keV such that the peak concentration is at a different depth than that of the n-type semiconductor, and in the dose range of about 8·

10E12 to 8·

10E13 cm-2 to overcompensate the n-type semiconductor doping and to create a region of the opposite conductivity type.

33. The method according to claim 26 wherein said net n-type doping of low concentration comprises a peak concentration of about 1 to 6 E17 cm-3 below the p-n junctions of said transistor'"'"'s deep source and drain regions.