High performance silicon contact for flip chip
First Claim
1. A method of forming coaxial integrated circuitry interconnect lines comprising:
- providing a substrate having front and back surfaces;
forming a hole with sidewalls extending through said substrate from said front to said back surface;
forming an outer conductive coaxial sheath on said sidewalls;
forming a coaxial dielectric layer radially inward and over said outer conductive coaxial sheath; and
forming an inner coaxial fine radially inward and over said coaxial dielectric layer.
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Abstract
The present invention provides a semiconductive substrate which includes front and back surfaces and a hole which extends through the substrate and between the front and back surfaces. The hole is defined in part by an interior wall portion and forms an outer conductive sheath. Conductive material is formed proximate at least some of the interior wall portion. Subsequently, a layer of dielectric material is formed within the hole, over and radially inwardly of the conductive material. A second conductive material is then formed within the hole over and radially inwardly of the dielectric material layer. The latter conductive material constitutes an inner conductive coaxial line component.
77 Citations
53 Claims
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1. A method of forming coaxial integrated circuitry interconnect lines comprising:
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providing a substrate having front and back surfaces;
forming a hole with sidewalls extending through said substrate from said front to said back surface;
forming an outer conductive coaxial sheath on said sidewalls;
forming a coaxial dielectric layer radially inward and over said outer conductive coaxial sheath; and
forming an inner coaxial fine radially inward and over said coaxial dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. An integrated circuitry interconnect line comprising:
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a substrate having front and back surfaces;
a hole with sidewalls extending through said substrate from said front to said back surface;
an outer conductive coaxial sheath formed on said sidewalls;
a coaxial dielectric layer formed radially inward and over said outer coaxial line; and
a conductive inner coaxial line formed radially inward and over said coaxial dielectric layer. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A processor system comprising:
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a processor; and
an integrated circuit coupled to said processor, at least one of said integrated circuit and processor comprising;
a substrate having front and back surfaces and a hole with sidewalls extending through said substrate from said front to said back surface;
a conductive outer coaxial sheath formed on said sidewalls;
a coaxial dielectric layer formed radially inward and over said outer coaxial sheath; and
a inner conductive coaxial line formed radially inward and over said coaxial dielectric layer. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
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42. A integrated circuit package comprising:
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a substrate supporting at least one integrated circuit chip, said substrate having front and back surfaces and at least a hole with sidewalls extending through said substrate from said front to said back surface;
an outer conductive coaxial sheath formed on said sidewalls;
a coaxial dielectric layer formed radially inward and over said outer conductive coaxial sheath; and
an inner conductive coaxial line formed radially inward and over said coaxial dielectric layer; and
a package which encases said substrate and said at least one chip. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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Specification