Minimizing event scheduling overhead in VHDL simulation
First Claim
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1. A method to reduce overhead of event scheduling for VHDL simulation, in a computer system, comprise:
- static analysis of the VHDL input descriptions and the characteristics of VHDL signals before executing the simulation to remove that do not affect values of the signals value, i.e. remove non-real events. To remove the non-real events and schedule real events for simulating the VHDL, the first two conditions were applied, which are described in the preferred embodiment;
dynamic check of the third condition for scheduling real events while removing the non-real events, by comparing the current value of the signal and the right hand sided value—
previous value of the signal—
as described in the preferred embodiment.
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Abstract
A method for minimizing event scheduling overhead in VHDL simulation were proposed, and the speed-up of the VHDL simulation time can be obtained. It consists of the two ideas. The first idea excludes any events that do not have any effects on VHDL simulation. The second idea is grouping multiple homogeneous events, and treating them as a single event to reduce the burden of scheduling in the simulation. These idea were applied separately as well as in a combined way.
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2 Claims
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1. A method to reduce overhead of event scheduling for VHDL simulation, in a computer system, comprise:
- static analysis of the VHDL input descriptions and the characteristics of VHDL signals before executing the simulation to remove that do not affect values of the signals value, i.e. remove non-real events. To remove the non-real events and schedule real events for simulating the VHDL, the first two conditions were applied, which are described in the preferred embodiment;
dynamic check of the third condition for scheduling real events while removing the non-real events, by comparing the current value of the signal and the right hand sided value—
previous value of the signal—
as described in the preferred embodiment. - View Dependent Claims (2)
- static analysis of the VHDL input descriptions and the characteristics of VHDL signals before executing the simulation to remove that do not affect values of the signals value, i.e. remove non-real events. To remove the non-real events and schedule real events for simulating the VHDL, the first two conditions were applied, which are described in the preferred embodiment;
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Current Assignee</Aen><Aes, Andy Huang, ACAD Corp. (Synopsys Incorporated)
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Original AssigneeAndy Huang, ACAD Corp. (Synopsys Incorporated)
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InventorsHuang, Andy
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Application NumberUS10/063,627Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current703/17CPC Class CodesG06F 30/33 Design verification, e.g. f...
