System and method for multi-bit flash reads using dual dynamic references

• US 20030208663A1
• Filed: 05/01/2002
• Published: 11/06/2003
• Est. Priority Date: 04/12/2002
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: AMD Investments Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Van Buskirk, Michael A., Hamilton, Darlene G., Chen, Pua-Ling, Kuribara, Kazuhiro
• Granted Patent: US 6,799,256 B2
• Time in Patent Office: Days
• US Class Current: 711/156
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A system and methodology is provided for proper reading of multi-bit memory cells in a memory device. A first reference cell and a second reference cell is employed to determine an average dynamic reference value. The average dynamic reference value is determined by reading a programmed bit of the first reference cell and reading an unprogrammed or erased bit of a second reference cell to determine an average dynamic reference value. The average dynamic reference value can be utilized to determine whether data cells are in a programmed state or in an unprogrammed state.

Claims

1. A multi-bit memory system, comprising:

a reference component that reads a programmed bit value from a first multi-bit reference cell and an unprogrammed bit value from a second multi-bit reference cell to determine an average dynamic reference value; and

a comparison component that employs the average dynamic reference value to facilitate determination of a program state for a bit of at least one multi-bit data cell.

2. The system of claim 1, the state is a programmed state.

3. The system of claim 1, the state is an unprogrammed state.

4. The system of claim 1 further comprising a sector of multi-bit data cells organized in rows and columns with associated wordlines attached to the multi-bit data cells in a row and with associated bitlines attached to the multi-bit data cells in a column, and the first and second multi-bit reference cell forming a multi-bit reference pair that is programmed and erased with the multi-bit data cells during programming and erase cycles.

5. The system of claim 4, the multi-bit reference pair is associated with a word in a wordline, the reference component utilizes the multi-bit reference pair during reading of bits in the word.

6. The system of claim 4, the multi-bit reference pair is associated with multi-bit data cells in a wordline, the reference component utilizes the multi-bit reference pair during reading of bits in the wordline.

7. The system of claim 4, further comprising a plurality of multi-bit reference pairs associated with and attached to a corresponding wordline, the reference component utilizes an associated multi-bit reference pair during reading of bits in the corresponding wordline.

8. The system of claim 4, the multi-bit reference pair is associated with multi-bit data cells in the sector, the reference component utilizes the multi-bit reference pair during reading of bits in the sector.

9. The system of claim 1, the first reference cell tracks charge loss associated with the at least one multi-bit data cell over program and erase cycles and the second reference cell tracks effects of complimentary bit disturb associated with the at least one multi-bit data cell over program and erase cycles.

10. The system of claim 4, the sector of multi-bit data cells and the multi-bit reference pair being ONO dual bit data cells.

11. The system of claim 1, the average dynamic reference value being one of an average read current and an average threshold voltage.

12. The system of claim 1, the reference component determines that the bit in the at least one multi-bit data cell is a programmed bit if it has a read value above the average dynamic reference value and is an unprogrammed bit if it has a read value below the average dynamic reference value.

13. An integrated circuit comprising the system of claim 1.

14. A computer comprising the system of claim 1.

15. An electronic device comprising the system of claim 1.

16. A system for reading bits in an array of dual bit flash memory cells, the dual bit memory cells having a normal bit and a complimentary bit associated with the normal bit, the system comprising:

a memory array having a plurality of dual bit data cells;

a reference array having a plurality of dual bit reference cells; and

a controller that determines an average read value of a programmed bit of a first reference cell and an unprogrammed bit of a second reference cell to determine if a bit in at least one of the dual bit data cells is in one of a programmed state and an unprogrammed state.

17. The system of claim 16, the controller programs the first reference cell to have a programmed bit and an unprogrammed bit and the second reference cell to have a programmed bit and an unprogrammed bit.

18. The system of claim 16, the reference array comprises a first dynamic reference array having dual bit reference cells utilized in tracking charge loss associated with program and erase cycles and a second dynamic reference array utilized to track effects of complimentary bit disturb on unprogrammed bits associated with program and erase cycles.

19. The system of claim 16, the plurality of dual bit reference cells of the reference array are programmed and erased with the plurality of dual bit data cells of the memory array during programming and erase cycles, such that the dual bit reference cells are the same age as the dual bit data cells.

20. The system of claim 16, the reference array includes a first reference cell and a second reference cell associated with each wordline in the sector.

21. The system of claim 16, the reference array includes a first reference cell and a second reference cell associated with each word in the sector.

22. The system of claim 16, further comprising a comparison component that compares the average read value with a read value from at least one bit of a dual bit data cell to determine if the at least one bit is in one of a programmed state and an unprogrammed state.

23. The system of claim 16, the programmed bit of the first reference cell is one of a normal bit and a complimentary bit and the unprogrammed bit of the second reference cell is one of a normal bit and a complimentary bit.

24. The system of claim 16, the memory array comprising a plurality of sectors and the reference array comprising a plurality of dynamic reference arrays, such that a dynamic reference array is associated with each of the plurality of sectors.

25. The system of claim 16, the controller programs one bit of the first reference cell and programs one bit of the second memory cell after executing a program and erase routine on the memory array and the reference array.

26. A method for reading bits in an array of multi-bit flash memory cells, the method comprising:

determining a first read value from a programmed bit of a first reference cell and a second read value from an unprogrammed bit of a second reference cell;

evaluating an average threshold value from the first read value and the second read value;

reading a bit of a data cell to determine a data bit read value;

comparing the data bit read value with the average threshold value; and

determining if the bit is one of a programmed bit and an unprogrammed bit based on the comparison.

27. The method of claim 26, the average threshold value being one of an average read current and an average threshold voltage.

28. The method of claim 27, further comprising performing a programming and erase cycle on the data cell and the first reference cell and the second reference cell.

29. The method of claim 28, further comprising programming a first bit of the first reference cell and programming a first bit of the second reference cell after performing a programming and erase cycle.

30. The method of claim 28, further comprising entering a normal operation where data cells are programmed prior to determining a first read value from a programmed bit of a first reference cell and a second read value from an unprogrammed bit of a second reference cell.

31. The method of claim 26, the array of multi-bit flash memory cells comprising a dual bit memory cell array formed from an ONO architecture.

32. The method of claim 26, the average threshold value is compared with bits in one of a word and a wordline to determine if a bit is in one of a programmed state and an unprogrammed state.

33. A system for reading dual bit flash memory cells, a dual bit memory cell having a normal bit and a complimentary bit associated with the normal bit, the system comprising:

means for programming bits in a dual bit memory array;

means for programming a first bit in a first reference cell and a second bit in a second reference cell, such that the first reference cell has a programmed bit and an unprogrammed bit and the second reference cell has a programmed bit and an unprogrammed bit;

means for determining an average read value associated with the programmed bit of the first reference cell and an unprogrammed bit of the second reference cell;

means for determining a bit read value of a bit in the dual bit memory array; and

means for comparing the bit read value with the average read value to determine if a bit is in one of a programmed state and an unprogrammed state.

34. The system of claim 33, further comprising means for performing a program and erase cycle on data bits in the memory array and reference bits in the reference cells.

35. The system of claim 34, the average read value being one of an average read current and an average threshold voltage.

36. The system of claim 34, the means for comparing the bit read value with the average read value to determine if a bit is in one of a programmed state and an unprogrammed state determines if the bit read value is above the average read value to define a programmed state and if the bit read value is below the average read value to define an unprogrammed state.