Apparatus having adjustable operational modes and method therefore

• US 20030210026A1
• Filed: 06/10/2003
• Published: 11/13/2003
• Est. Priority Date: 08/21/2000
• Status: Active Grant

• Current Assignee: Ali Minaei, Gregory B. Tucker, Jay Heeb, Lawrence T. Clark, Michael W. Morrow, Yuan-Po Ypt Tseng
• Original Assignee: Ali Minaei, Gregory B. Tucker, Jay Heeb, Lawrence T. Clark, Michael W. Morrow, Yuan-Po Ypt Tseng
• Inventors: Ypt Tseng, Yuan-Po, Clark, Lawrence T., Morrow, Michael W., Heeb, Jay, Tucker, Gregory B., Minaei, Ali
• Granted Patent: US 6,949,918 B2
• Time in Patent Office: Days
• US Class Current: 323/351
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator and a clock divider that may be used to adjust the operational frequency and/or voltage potential of the integrated circuit to reduce the power consumption of the integrated circuit while in operation.

Claims

1. An apparatus comprising:

a dynamic random access memory; and

a processor coupled to the static random access memory, the processor comprising;

a phase lock loop adapted to provide an output signal;

a first divider adapted to receive the output signal from the phase lock loop; and

a second divider adapted to receive the output signal from the phase lock loop and provide an output signal.

2. The apparatus of claim 1, wherein the second divider of the processor is further adapted to provide the output signal to at least two transistors.

3. The apparatus of claim 2, wherein the first divider of the processor is further adapted to provide an output signal and the phase lock loop is adapted to receive the output signal of the first divider.

4. The apparatus of claim 3, wherein the phase lock loop of the processor is not adapted to receive the output signal of the second divider.

5. The apparatus of claim 1, wherein the processor further comprises a level shifter coupled to the phase lock loop and the second divider.

6. The apparatus of claim 5, wherein the level shifter of the processor is adapted to receive the output signal of the phase lock loop and to provide the second divider with an input signal.

7. The apparatus of claim 1, wherein the phase lock loop of the processor is adapted to operate in a first voltage domain region and the second divider is adapted to operate in a second voltage domain region.

8. The apparatus of claim 7, wherein the processor is further adapted to adjust the voltage potential in the second voltage domain region with respect to the first voltage domain region while the processor is in operation.

9. The apparatus of claim 1, wherein the processor further comprises a voltage regulator adapted to provide an interrupt signal.

11. The integrated circuit of claim 10, wherein the phase lock loop is not coupled to an output signal of the clock divider.

12. The integrated circuit of claim 10, wherein the feedback loop is adapted to provide an output signal that is out of phase with respect to an output signal of the clock divider.

14. The integrated circuit of claim 13, wherein the core logic is not coupled to the output signal of the feedback loop.

17. The method of claim 16, wherein reducing the frequency includes reducing the frequency to at least a portion of a processor while the processor is executing an user application.

10. An integrated circuit comprising:

a phase lock loop adapted to provide an output signal to a feedback divider and a clock divider, wherein the phase lock loop is adapted to receive an output signal of the feedback divider.

13. The integrated circuit of claim 10, further comprising core logic coupled to receive an output signal from the clock divider.

15. A method comprising:

reducing the frequency of a clock signal to at least a portion of a processor while the processor is in operation.

16. The method of claim 15, wherein reducing the frequency includes reducing the frequency to at least a portion of a processor while the processor is executing an instruction.

18. The method of claim 15, further comprising reducing an operational voltage range to at least a portion of the processor while the processor is in operation.

19. The method of claim 15, further comprising providing a clock signal to a clock divider and a feedback divider with a phase lock loop.

20. The method of claim 19, wherein reducing the frequency of the clock signal includes reducing an output signal of the clock divider.

21. The method of claim 20, wherein reducing the output signal of the clock divider includes while substantially maintaining an output signal of the feedback divider.

22. A method of reducing the amount of power consumed by a processor, the processor having a phase lock loop and a clock divider, the method comprising:

reducing the frequency of an output of the clock divider while substantially maintaining the frequency of an input signal to the phase lock loop.

23. The method of claim 22, wherein the processor includes a feedback divider, and substantially maintaining the frequency of the input signal to the phase lock loop includes substantially maintaining the frequency of an output signal of a feedback loop.

24. The method of claim 22, further comprising maintaining operation of at least a portion of the processor while reducing the frequency of the output of the clock divider.

25. The method of claim 24, further comprising reducing a voltage range to at least a portion of the processor.

26. The method of claim 25, further comprising raising the voltage range to at least a portion of the processor.

27. The method of claim 26, further comprising generating an interrupt signal to halt operation of at lest a portion of a first process executing with the processor.

28. The method of claim 26, wherein generating the interrupt signal further comprises substantially simultaneously executing a second process with the processor.

29. An article comprising:

a storage medium having stored thereon instructions, that, when executed by a computing platform, results in;

reducing the frequency of a clock divider; and

maintaining the frequency of an output signal of a feedback divider.

30. The article of claim 29, wherein the instructions, when executed, further result in lowing the voltage range to at least a portion of the computing platform.

31. The article of claim 29, wherein the instructions, are executed, upon receiving an interrupt signal from a voltage regulator.

32. An integrated circuit comprising:

a phase lock loop adapted to provide an output signal to a feedback divider and a clock divider, wherein the phase lock loop is adapted to receive an output signal of the feedback divider, and the clock divider is adapted to provide at least two clock signals of different frequency.

33. The integrated circuit of claim 32, wherein the clock divider is adapted to provide the at least two clock signals to different portions of the integrated circuit.

34. The integrated circuit of claim 32, wherein the feedback loop is adapted to provide an output signal that is out of phase with respect to an output signal of the clock divider.