Intermesh memory device

• US 20030210567A1
• Filed: 05/07/2002
• Published: 11/13/2003
• Est. Priority Date: 05/07/2002
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Van Brocklin, Andrew L., Fricke, Peter, Koll, Andrew
• Granted Patent: US 6,842,369 B2
• Time in Patent Office: Days
• US Class Current: 365/174
• CPC Class Codes: G11C 17/00 Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

An intermesh memory device includes memory components that each have a determinable resistance value and electronic switches that each control current through one or more of the memory components such that a potential is applied to the memory components. A first electronic switch of the intermesh memory device is electrically coupled to an input of a memory component and a second electronic switch is electrically coupled to an output of the memory component. The first electronic switch and the second electronic switch are configured together to apply a potential to the memory component.

Claims

1. An intermesh memory device, comprising:

memory components each configured to have a determinable resistance value, the memory components forming a memory array with a first set of the memory components substantially perpendicular to a second set of the memory components;

electronic switches each configured to control current through one or more of the memory components such that a potential is applied to the one or more memory components;

wherein a first electronic switch is electrically coupled to drive an input of a memory component and a second electronic switch is electrically coupled to sense an output of the memory component, the first electronic switch and the second electronic switch configured together to apply a potential to the memory component.

2. An intermesh memory device as recited in claim 1, wherein the memory components form a first region and the electronic switches form a second region, the first region offset from the second region.

3. An intermesh memory device as recited in claim 1, wherein the memory components form a first region and the electronic switches form a second region, the first region offset from the second region with electrically conductive vias each configured to electrically couple one or more of the memory components to one or more of the electronic switches.

4. An intermesh memory device as recited in claim 1, wherein the memory components form a first region and the electronic switches form a second region, the first region offset from the second region and the first region substantially parallel to the second region.

5. An intermesh memory device as recited in claim 1, wherein the first set of the memory components are offset from the second set of the memory components.

6. An intermesh memory device as recited in claim 1, wherein the first electronic switch is electrically coupled to drive an input of at least a second memory component and a third electronic switch is electrically coupled to sense an output of the second memory component, the first electronic switch and the third electronic switch configured together to apply a potential to the second memory component.

7. An intermesh memory device as recited in claim 1, wherein one or more of the electronic switches are voltage controlled switches.

8. An intermesh memory device as recited in claim 1, wherein a first set of the electronic switches are p-channel field effect transistors and wherein a second set of the electronic switches are n-channel field effect transistors.

9. An intermesh memory device as recited in claim 1, wherein the first electronic switch is an n-channel field effect transistor and the second electronic switch is a p-channel field effect transistor.

10. An intermesh memory device as recited in claim 1, wherein an individual memory component is formed with electrically resistive material configured to indicate the determinable resistance value when the potential is applied to the individual memory component.

11. An intermesh memory device as recited in claim 1, wherein an individual memory component includes a resistor device.

12. An intermesh memory device as recited in claim 1, wherein an individual memory component includes an anti-fuse device.

13. An intermesh memory device as recited in claim 1, wherein an individual memory component includes an anti-fuse device electrically coupled with a control element.

14. An intermesh memory device as recited in claim 1, wherein an individual memory component includes an anti-fuse device configured to indicate a resistance value corresponding to a logic state when the potential is applied to the individual memory component.

15. An intermesh memory device as recited in claim 1, wherein an individual memory component includes an anti-fuse device electrically coupled with a control element, the anti-fuse device being configured to indicate a first resistance value corresponding to a first logic state, and the anti-fuse device being configurable to indicate a second resistance value corresponding to a second logic state.

16. An intermesh memory device as recited in claim 1, further comprising one or more sense amplifiers each configured to determine the resistance value of one or more of the memory components.

17. An integrated circuit comprising the intermesh memory device as recited in claim 1.

18. An electronic device comprising the intermesh memory device as recited in claim 1.

19. A portable computing device comprising the intermesh memory device as recited in claim 1.

20. A printing device comprising the intermesh memory device as recited in claim 1.

21. An electrical structure, comprising:

electronic switches fabricated in a semiconductive material on a semiconductor substrate;

electrically resistive components fabricated in a device region offset from the semiconductive material, the electrically resistive components configured to form an intermesh array of memory cells formed with a first set of the electrically resistive components intersected by a second set of the electrically resistive components;

electrically conductive vias configured to electrically couple one or more of the electronic switches to one or more of the electrically resistive components.

22. An electrical structure as recited in claim 21, wherein the electrically resistive components are offset over the electronic switches.

23. An electrical structure as recited in claim 21, wherein the first set of the electrically resistive components are offset from the second set of the electrically resistive components.

24. An electrical structure as recited in claim 21, wherein the first set of the electrically resistive components are fabricated in a first region and the second set of the electrically resistive components are fabricated in a second region, the first region offset from the second region and the first region substantially parallel to the second region.

25. An electrical structure as recited in claim 21, wherein a first electronic switch is electrically coupled to drive an electrically resistive component and a second electronic switch is electrically coupled to sense the electrically resistive component, the first electronic switch and the second electronic switch configured together to apply a potential to the electrically resistive component.

26. An electrical structure as recited in claim 21, wherein the electronic switches include a first set of p-channel field effect transistors and a second set of n-channel field effect transistors.

27. An electrical structure as recited in claim 21, wherein the electronic switches form an array of voltage controlled switches, the array including p-channel field effect transistors alternating with n-channel field effect transistors.

28. An electrical structure as recited in claim 21, wherein the electrically resistive components are each configured to indicate a determinable resistance value when a potential is applied to an individual electrically resistive component.

29. An electrical structure as recited in claim 21, wherein the electrically resistive components include a programmable anti-fuse device.

30. An electrical structure as recited in claim 21, wherein the electrically resistive components include a programmable anti-fuse device electrically coupled with a control element.

31. An integrated circuit comprising the electrical structure as recited in claim 21.

32. A method, comprising:

forming electronic switches on a semiconductor substrate;

forming electrically conductive vias;

forming memory components in an intermesh array, an individual memory component being electrically coupled to a first electronic switch with a first electrically conductive via and the individual memory component being electrically coupled to a second electronic switch with a second electrically conductive via.

33. A method as recited in claim 32, further comprising determining a resistance value of a memory component when a potential is applied to the memory component.

34. A method as recited in claim 32, further comprising determining a resistance value of a memory component when the first electronic switch and the second electronic switch are together controlled to apply a potential to the memory component.

35. A method as recited in claim 32, further comprising associating a logic state of a data bit with a resistance value of a memory component.

36. A method as recited in claim 32, wherein forming the electronic switches includes forming the electronic switches with field effect transistors.

37. A method as recited in claim 32, wherein forming the electronic switches includes forming the electronic switches with alternating p-channel field effect transistors and n-channel field effect transistors.

38. A method as recited in claim 32, wherein forming the electronic switches includes forming the electronic switches with voltage controlled switches.

39. A method as recited in claim 32, wherein forming the memory components includes forming the memory components in a device region that is offset from the semiconductor substrate.

40. A method as recited in claim 32, wherein forming the memory components includes forming the memory components with electrically resistive material.

41. A method as recited in claim 32, wherein forming the memory components includes forming the memory components with an anti-fuse device.

42. A method as recited in claim 32, wherein forming the memory components includes forming the memory components with an anti-fuse device electrically coupled with a control element.

43. A method as recited in claim 32, wherein forming the memory components includes forming a first array of memory components intersecting with a second array of memory components.

44. A method as recited in claim 32, wherein forming the memory components includes forming a first array of memory components being substantially perpendicular with a second array of memory components.

45. A method as recited in claim 32, further comprising programming the resistance value of individual memory components by applying a voltage to the individual memory components.

46. A method as recited in claim 32, further comprising configuring the resistance value of individual memory components by exposing the individual memory components to light.

47. A method as recited in claim 32, further comprising configuring the resistance value of individual memory components by exposing electrically resistive material forming the individual memory components to light.

48. A method as recited in claim 32, further comprising configuring the resistance value of individual memory components by exposing the individual memory components to heat.

49. A method as recited in claim 32, further comprising configuring the resistance value of individual memory components by exposing electrically resistive material forming the individual memory components to heat.

50. An electronic device, comprising:

means for applying a drive voltage with a drive pillar coupled to drive an input of a first memory component in an intermesh memory device;

means for applying a sense voltage with a sense pillar coupled to sense an output of the first memory component; and

means for sensing a resistance value of the first memory component, the resistance value being determinable when the drive pillar and the sense pillar are enabled.

51. An electronic device as recited in claim 50, further comprising:

means for applying the drive voltage with the drive pillar coupled to drive an input of a second memory component in the intermesh memory device;

means for applying the sense voltage with a second sense pillar coupled to sense an output of the second memory component; and

means for sensing a resistance value of the second memory component, the resistance value being determinable when the drive pillar and the second sense pillar are enabled.

52. An electronic device, comprising:

means for enabling a first electronic switch coupled to apply a drive voltage to an input of a row memory component in an intermesh memory device;

means for enabling a second electronic switch coupled to apply a sense voltage to an output of the row memory component; and

means for sensing a resistance value of the row memory component, the resistance value being determinable when the first electronic switch and the second electronic switch are enabled.

53. An electronic device as recited in claim 52, further comprising:

means for enabling the first electronic switch coupled to apply a drive voltage to an input of a column memory component in the intermesh memory device;

means for enabling a third electronic switch coupled to apply a sense voltage to an output of the column memory component; and

means for sensing a resistance value of the column memory component, the resistance value being determinable when the first electronic switch and the third electronic switch are enabled.

54. A method, comprising:

applying a first voltage to an input of a first memory component in an intermesh memory device, the first voltage being applied with a drive pillar coupled to the input of the first memory component;

applying a second voltage to an output of the first memory component, the second voltage being applied with a sense pillar coupled to the output of the first memory component; and

sensing a resistance value of the first memory component, the resistance value being determinable when the drive pillar and the sense pillar apply a potential to the first memory component.

55. A method as recited in claim 54, further comprising:

applying the first voltage to an input of a second memory component in the intermesh memory device, the first voltage being applied with the drive pillar coupled to the input of the second memory component;

applying the second voltage to an output of the second memory component, the second voltage being applied with a second sense pillar coupled to the output of the second memory component; and

sensing a resistance value of the second memory component, the resistance value being determinable when the drive pillar and the second sense pillar apply a potential to the second memory component.

56. A method as recited in claim 54, further comprising:

turning on a first electronic switch coupled to the drive pillar to apply the first voltage to the input of the first memory component; and

turning on a second electronic switch coupled to the sense pillar to apply the second voltage to the output of the first memory component.

57. A method as recited in claim 55, further comprising:

turning on a first electronic switch coupled to the drive pillar to apply the first voltage to the input of the second memory component; and

turning on a second electronic switch coupled to the second sense pillar to apply the second voltage to the output of the second memory component.

58. A method as recited in claim 54, further comprising:

applying the first voltage to an input of a second memory component in an intermesh memory device, the first voltage being applied with a second drive pillar coupled to the input of the second memory component;

applying the second voltage to an output of the second memory component, the second voltage being applied with a second sense pillar coupled to the output of the second memory component; and

sensing a resistance value of the second memory component, the resistance value being determinable when the second drive pillar and the second sense pillar apply a potential to the second memory component.

59. A method as recited in claim 58, further comprising:

turning on a first electronic switch coupled to the drive pillar to apply the first voltage to the input of the first memory component;

turning on a second electronic switch coupled to the second drive pillar to apply the first voltage to the input of the second memory component;

turning on a third electronic switch coupled to the sense pillar to apply the second voltage to the output of the first memory component; and

turning on a fourth electronic switch coupled to the second sense pillar to apply the second voltage to the output of the second memory component.

60. A method as recited in claim 58, further comprising:

turning on a first electronic switch coupled to the drive pillar to apply the first voltage to the input of the first memory component and coupled to the second drive pillar to apply the first voltage to the input of the second memory component; and

turning on a second electronic switch coupled to the sense pillar to apply the second voltage to the output of the first memory component and coupled to the second sense pillar to apply the second voltage to the output of the second memory component.