Nonvolatile memory device with a non-planar gate-insulating layer and method of fabricating the same

• US 20030211689A1
• Filed: 04/22/2003
• Published: 11/13/2003
• Est. Priority Date: 05/07/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yoo, Hyun-khe, Han, Jeong-uk
• Granted Patent: US 7,038,270 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory device with a non-planar gate insulating layer and a method of fabricating the same are provided. The device includes a tunnel insulating pattern, a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked. A lower insulating pattern, which is covered with the charge storage layer and thicker than the tunnel insulating pattern, is disposed on the semiconductor substrate beside the tunnel insulating layer. A heavily doped region including impurities of the same type as the semiconductor substrate is disposed in the semiconductor substrate under the tunnel insulating pattern.

Claims

1. A non-volatile memory device comprising:

a semiconductor substrate of a first conductivity type;

a charge storage layer, an upper insulating layer and a control gate electrode which are sequentially stacked on the semiconductor substrate;

a lower insulating pattern and a tunnel insulating pattern interposed between the charge storage layer and the semiconductor substrate; and

a heavily doped region of the first conductivity type formed in the semiconductor substrate under the tunnel insulating pattern, wherein the tunnel insulating pattern is thinner than the lower insulating pattern in thickness and disposed at the side of the lower insulating pattern.

2. The device as recited in claim 1, further comprising source/drain regions of a second conductivity type which are formed in the semiconductor substrate on opposite sides of the control gate electrode.

3. The device as recited in claim 2, wherein the source/drain regions have a lightly doped drain structure.

4. The device as recited in claim 2, wherein the tunnel insulating pattern is disposed adjoining the drain region.

5. The device as recited in claim 1, further comprising a lightly doped region formed in the surface of the semiconductor substrate, wherein the lightly doped regions have the first conductivity type and are formed under the tunnel insulating pattern.

6. The device as recited in claim 2, wherein the heavily doped region of the first conductivity type surround a lower side of the drain region.

7. The device as recited in claim 1, wherein the lower insulating pattern is a silicon oxide layer.

8. The device according as recited in claim 1, wherein the charge storage layer is a silicon nitride layer.

9. The device as recited in claim 1, wherein the upper insulating layer is a silicon oxide layer or a high-k dielectric layer.

10. A method of fabricating the non-volatile memory device comprising:

forming a lower insulating pattern on a semiconductor substrate of a first conductivity type;

forming a tunnel insulating layer on the semiconductor substrate beside the lower insulating pattern;

sequentially forming a charge storage layer, an upper insulating layer and a gate conductive layer on the semiconductor substrate; and

patterning the gate conductive layer to form a control gate electrode, wherein the control gate electrode is placed over the lower insulating pattern and the tunnel insulating layer and parallel to the lower insulating pattern, and wherein the tunnel insulating layer is formed to a thickness thinner than that of the lower insulating pattern.

11. The method according to claim 10, wherein forming the lower insulating pattern comprises:

forming a lower insulating layer on the semiconductor substrate;

forming a photoresist pattern on the lower insulating layer;

etching the lower insulating layer using the photoresist pattern as an etching mask; and

removing the photoresist pattern.

12. The method according to claim 10, further comprising forming a lightly doped region of a first conductivity type in the semiconductor substrate under the tunnel insulating layer before forming the tunnel insulating layer.

13. The method according to claim 10, further comprising forming a heavily doped region of a first conductivity type in the semiconductor substrate under the tunnel insulating layer before forming the tunnel insulating layer.

14. The method according to claim 10, wherein the lower insulating pattern and the tunnel insulating layer are formed of a silicon oxide layer.

15. The method according to claim 10, wherein the charge storage layer is formed of a silicon nitride layer.

16. The method according to claim 15, wherein forming the silicon nitride layer is performed with a nitrification including a chemical vapor deposition or a thermal treatment process.

17. The method according to claim 16, wherein the nitrification uses gases including nitrogen such as N₂O or NO.

18. The method according to claim 10, wherein the upper insulating layer is a silicon oxide layer or a high-k dielectric layer.

19. The method according to claim 10, further comprises patterning the upper insulating layer, the charge storage layer, the lower insulating layer and the tunnel insulating layer after forming the control gate electrode.