Methods and apparatus for responding to a request cluster

• US 20030212741A1
• Filed: 05/13/2002
• Published: 11/13/2003
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: Sanmina-SCI Corporation
• Original Assignee: Newisys, Inc. (Sanmina-SCI Corporation)
• Inventors: Glasco, David B.
• Granted Patent: US 7,395,379 B2
• Time in Patent Office: Days
• US Class Current: 709/203
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 2212/507 using speculative control

Abstract

According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A home cluster of processors receives a cache access request from a request cluster. The home cluster includes mechanisms for instructing probed remote clusters to respond to the request cluster instead of to the home cluster. The home cluster can also include mechanisms for reducing the number of probes sent to remote clusters. Techniques are also included for providing the requesting cluster with information to determine the number of responses to be transmitted to the requesting cluster as a result of the reduction in the number of probes sent at the home cluster.

Claims

1. A computer system, comprising:

a home cluster including a first plurality of processors and a home cache coherence controller, the first plurality of processors and the home cache coherence controller interconnected in a point-to-point architecture;

wherein the home cache coherence controller is configured to send a probe to a remote cluster upon receiving a cache access request from a request cluster, wherein the probe includes information directing the remote cluster to send a probe response corresponding to the request to the request cluster.

2. The computer system of claim 1, wherein the cache access request includes a first tag identifying the request cluster and a node in the request cluster.

3. The computer system of claim 2, wherein the probe includes a second tag identifying the request cluster and the node in the request cluster.

4. The computer system of claim 3, wherein the second tag is an instance of the first tag.

5. The computer system of claim 3, wherein the second tag and the first tag occupy the same tag field.

6. The computer system of claim 3, wherein the second tag is included in the probe after the home cache coherence controller accesses a pending buffer.

7. The computer system of claim 2, wherein the probe is associated with the memory line corresponding to the cache access request.

8. The computer system of claim 2, wherein the probe is sent after the cache access request is ordered at a serialization point in the home cluster.

9. The computer system of claim 8, wherein the request cluster receives probe responses from the remote cluster and the home cluster.

10. The computer system of claim 9, wherein the request cluster also receives a request response corresponding to the request from the home cluster.

11. A computer system, comprising:

a first cluster including a first plurality of processors and a first cache coherence controller, the first plurality of processors and the first cache coherence controller interconnected in a point-to-point architecture;

a second cluster including a second plurality of processors and a second cache coherence controller, the second plurality of processors and the second cache coherence controller interconnected in a point-to-point architecture, the first cache coherence controller coupled to the second cache coherence controller and configured to send a request to the second cluster;

wherein the first cache coherence controller is configured to receive a plurality of probe responses corresponding to the request.

12. The computer system of claim 11, wherein the request identifies a node in the first cluster.

13. The computer system of claim 11, wherein the plurality of probe responses corresponding to the request include a plurality of tags identifying the node in the first cluster.

14. The computer system of claim 11, wherein the number of probe responses corresponds to the number of clusters in a multiprocessor system.

15. The computer system of claim 14, wherein the number of probe responses corresponds to the type of transaction associated with the cache access request.

16. The computer system of claim 11, wherein the first cluster is a request cluster.

17. The computer system of claim 16, wherein the second cluster is a home cluster.

18. The computer system of claim 17, wherein a third cluster is a remote cluster.

19. The computer system of claim 18, wherein the plurality of probe responses comprise responses from the home cluster and the remote cluster.

20. A method for a cache coherence controller to manage data access in a multiprocessor system, the method comprising:

sending a cache access request originating from a first cluster of processors to a second cluster of processors;

receiving a plurality of probe responses corresponding to the cache access request from a plurality of clusters.

21. The method of claim 20, wherein the plurality of clusters comprises the second cluster and a third cluster.

22. The method of claim 20, wherein the second cluster is a home cluster.

23. The method of claim 20, wherein the third cluster is a remote cluster.

24. The method of claim 20, waiting for the plurality of probe responses before signaling a processor associated with the cache access request.

25. The method of claim 24, waiting for a predetermined number of probe responses before signaling the processor.

26. The method of claim 25, wherein the number of probe responses corresponds to the number of clusters in a multiprocessor system.

27. The method of claim 25, wherein the number of probe responses corresponds to the type of transaction associated with the cache access request.

28. A cache coherence controller in a multiprocessor system, the cache coherence controller comprising:

means for sending a cache access request originating from a first cluster of processors to a second cluster of processors;

means for receiving a plurality of probe responses corresponding to the cache access request from a plurality of clusters.

29. The cache coherence controller of claim 28, wherein the plurality of clusters comprises the second cluster and a third cluster.

30. The cache coherence controller of claim 28, wherein the second cluster is a home cluster.

31. The cache coherence controller of claim 28, wherein the third cluster is a remote cluster.

32. The cache coherence controller of claim 28, waiting for the plurality of probe responses before signaling a processor associated with the cache access request.

33. The cache coherence controller of claim 32, waiting for a predetermined number of probe responses before signaling the processor.

34. The cache coherence controller of claim 33, wherein the number of probe responses corresponds to the number of clusters in a multiprocessor system.

35. The cache coherence controller of claim 33, wherein the number of probe responses corresponds to the type of transaction associated with the cache access request.