Split computer architecture

• US 20030212755A1
• Filed: 03/06/2003
• Published: 11/13/2003
• Est. Priority Date: 10/30/1998
• Status: Active Grant

• Current Assignee: Vertiv IT Systems, Inc. (Vertiv Holdings Co.)
• Original Assignee: Cybex Computer Products Corporation (Vertiv Holdings Co.)
• Inventors: OʼBryant, Greg, Thomas, Christopher L., Luterman, Greg, Asprey, Robert R., Choun, Jeffrey E., Shatas, Remigius G.
• Granted Patent: US 7,020,732 B2
• Time in Patent Office: Days
• US Class Current: 709/217
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: H04L 67/01 Protocols
• CPC Class Codes: H04L 67/10 in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.

Claims

1. A remote-distance communications interface between a processor and physically disassociated peripheral controllers, comprising:

a first data bus onto which the processor communicates;

a second data bus, physically disassociated from the first data bus, onto which the associated peripheral controllers communicate; and

a bus interface coupling the first and second data buses to organize communication between said processor and said disassociated peripheral controllers and including at least one clock domain barrier between said first and second data buses.

2. An interface according to claim 1, wherein the bus interface includes a host interface coupled to the first data bus and a terminal interface coupled to the second data bus, and wherein said host interface and said terminal interface communicate via a common communication medium.

3. An interface according to claim 2, wherein:

the host interface further includes a first bridge coupled to the first data bus, and

the terminal interface further includes a second bridge coupled to the second data bus.

4. An interface according to claim 2, wherein:

the host interface includes at least one state machine and at least one temporary storage device, and

the terminal interface includes at least one other state machine and at least one other temporary storage device.

5. An interface according to claim 4, wherein:

the host interface includes;

a host master state machine and a host incoming temporary storage device together providing a unidirectional path from the communication medium to the first bridge, and

a host target state machine and a host outgoing temporary storage device together providing a unidirectional path from the first bridge to the communication medium; and

the terminal interface includes;

a terminal master state machine and a terminal incoming temporary storage device together providing a unidirectional path from the communication medium to the second bridge, and

a terminal target state machine and a terminal outgoing temporary storage device together providing a unidirectional path from the second bridle to the communication medium.

6. An interface according to claim 5, wherein the host incoming temporary storage device receives data packets from the terminal outgoing temporary storage device.

7. An interface according to claim 6, wherein the terminal incoming temporary storage device receives data packets from the host outgoing temporary storage device.

8. An interface according to claim 7, wherein terminal and host outgoing temporary storage devices retain a certain data packet after sending the certain data packet to, respectively, the host and terminal incoming temporary storage devices and clear said certain data packet only after said respective host and terminal incoming temporary storage devices return acknowledgments corresponding to said certain data packet.

9. An interface according to claim 3, wherein the host interface further includes a first FPGA coupled between the first bridge and the communication medium and the terminal interface further includes a second FPGA coupled between the second bridge and the communication medium.

10. An interface according to claim 9, wherein the first and second FPGAs further respectively include first and second FIFOs.

11. An interface according to claim 9, wherein the first and second FPGAs further respectively include first and second pairs of FPGAs.

12. An interface according to claim 3, wherein the host interface further includes a first ASIC coupled between the first bridge and the communication medium and the terminal interface further includes a second ASIC coupled between the second bridge and the communication medium.

13. An interface according to claim 12, wherein the first and second ASICs further respectively include first and second FIFOs.

14. An interface according to claim 12, wherein the first and second ASICs further respectively include first and second pairs of ASICs.

15. An interface according to claim 10, wherein the first and second pairs of FIFOs include buffers to store data already output onto the communication medium until receipt of said data is acknowledged.

16. An interface according to claim 10, wherein the first and second pairs of FIFOs include buffers to store data already output onto the communication medium and to repeat the stored data output when an acknowledgment is not received after a predetermined time.

17. An interface according to claim 5, wherein the host and terminal interfaces provide cut-through switching from the host and terminal outgoing storage devices.

18. An interface according to claim 17, wherein the host and terminal interfaces provide store-and-forward switching from the host and terminal incoming storage devices.

19. An interface according to claim 3, wherein the host interface further includes:

a host master state machine coupled to output to the first bridge;

a first FIFO outputting master bus data to the host master state machine;

a host incoming packet processor coupled to the communication medium to receive packets from the communication medium, format convert the packets and output the format converted packets to the first FIFO;

a host target state machine coupled to input target bus data from the first bridge;

a second FIFO receiving the target bus data from the host target state machine; and

a host outgoing packet processor coupled to the communication medium to format the target bus data from the second FIFO into packets and deliver the packets onto the is communication medium; and

wherein the terminal interface further includes;

a terminal master state machine coupled to output to the second bridge;

a third FIFO outputting master bus data to the terminal master state machine;

a terminal incoming packet processor coupled to the communication medium to receive packets from the communication medium, format convert the packets and output the format converted packets to the third FIFO;

a terminal target state machine coupled to input target bus data from the second bridge;

a fourth FIFO receiving the target bus data from the terminal target state machine; and

a terminal outgoing packet processor coupled to the communication medium to format the target bus data from the fourth FIFO into packets and deliver the packets onto the communication medium.

20. An interface according to claim 1, wherein the bus interface further includes a second clock domain barrier between said first and second data buses.

21. An interface according to claim 1, wherein the bus interface includes:

an assembler to receive packets of data from a communication medium and de-packet said data,

an in-FIFO to receive the de-packeted data and buffer said de-packeted data for destination onto the first bus;

an out-FIFO to receive interactive data from the second bus and buffer the interactive data; and

an outpacket engine to receive the interactive data from the out-FIFO, packet the interactive data into said packets of data received by the assembler and to output said packets of data to said assembler.

22. An interface according to claim 21, farther including:

a director to control operation of the assembler; and

a keymaster to control operation of the outpacket engine.

23. An interface according to claim 22, further including an outstanding queue circuit to index the interactive data delivered to the out-FIFO.

24. An interface according to claim 23, wherein the keymaster further issues an acknowledgment to the outpacket engine each time the in-FIFO buffers a corresponding one of said de-packeted data.

25. An interface according to claim 24, wherein the outpacket engine delivers said acknowledgment to the assembler, and said assembler thereby commands said outstanding queue circuit to remove said depacketed data corresponding to said acknowledgment from said index.

26. A computer system, comprising:

a processor;

an applications storage device operatively associated with the processor to provide the processor with applications routines;

local peripheral controllers operatively associated with user computer peripherals and interfacing said applications routines with said user computer peripherals;

a split data bus comprising;

a first data bus onto which the processor and applications storage device communicate;

a second data bus onto which the local peripheral controllers communicate; and

a bus interface coupling the first and second data buses and including at least one clock domain barrier between said first and second data buses.

27. An interface according to claim 26,

wherein the bus interface further includes a second clock domain barrier.

28. An interface according to claim 26,

wherein the local peripherals include two from the group consisting of:

a video controller;

a sound card;

a floppy drive; and

a PCI-compliant peripheral controller.

29. An interface according to claim 26, further including at least one user device comprising at least one of a keyboard and a pointing device, said user device producing user device signals input directly to said bus interface and passing to said first data bus without passing through said second data bus.

30. A method of communicating from a first data bus to a second data bus, comprising:

addressing interactive data from the first data bus to a first bridge;

passing the interactive data from the first bridge to a first logic device and in said first logic device;

a) buffering the interactive data in a first FIFO;

b) outputting the interactive data from the first FIFO across a clock domain barrier; and

c) continuing to store the interactive data after said step b);

packeting the interactive data into packet data;

delivering the packet data to a proximate portion of a long distance communication medium;

receiving the packet data at a distal portion of the long distance communication medium;

depacketing the packet data back into interactive data;

passing the interactive data to a second logic device and in said second logic device;

a) buffering the interactive data in a second FIFO; and

b) outputting the interactive data from the second FIFO across a clock domain barrier;

receiving the interactive data from the second logic device at a second bridge; and

addressing the interactive data from the second bridge to the second data bus.

31. An interface according to claim 30,

further including the step, after the step of buffering the interactive data in the second FIFO, of:

returning an acknowledgment to the first FIFO.

32. An interface according to claim 31, further including the step after the step of returning the acknowledgment of clearing the first FIFO.

33. An interface according to claim 30, further including the steps of:

addressing response interactive data from the second data bus to the second bridge;

passing the response interactive data from the second bridge to a third logic device and in said third logic device;

a) buffering the response interactive data in a third FIFO;

b) outputting the response interactive data from the third FIFO across a clock domain barrier; and

c) continuing to store the response interactive data after said step b);

packeting the response interactive data into response packet data;

delivering the response packet data to the distal portion of the long distance communication medium;

receiving the response packet data at the proximate portion of the long distance communication medium;

depacketing the response packet data back into response interactive data;

passing the response interactive data to a fourth logic device and in said fourth logic device;

a) buffering the response interactive data in a fourth FIFO; and

b) outputting the response interactive data from the fourth FIFO across a clock domain barrier;

receiving the response interactive data from the fourth logic device at the first bridge; and

addressing the response interactive data from the first bridge to the first data bus.

34. An interface according to claim 33,

further including the step, after the step of buffering the interactive data in the fourth FIFO, of;

returning an acknowledgment to the third FIFO.

35. An interface according to claim 34,

further including the step after the step of returning the acknowledgment of clearing the third FIFO.

36. An interface according to claim 30, further including the step of:

after passing, the interactive data to the second logic device, testing for an error condition in the step of buffering the interactive data in a second FIFO.

37. An interface according to claim 36, further including the step of returning a NACK to the first FIFO when said error condition is discovered.

38. An interface according to claim 33, further including the steps of:

after passing the interactive data to the second logic device, testing for an error condition in the step of buffering the interactive data in a second FIFO;

when said error condition is discovered, delivering a NACK response packet to the distal portion of the long distance a communication medium;

receiving the NACK response packet at the proximate portion of the long distance communication medium; and

delivering the NACK response packet to the first FIFO.

39. An interface according to claim 38, further including the steps of:

repeating the buffering, outputting and continuing steps in said first logic device when said NACK response is received by said first FIFO.

40. An interface according to claim 39, wherein the steps of repeating the buffering, outputting and continuing steps are repeated for all unacknowledged data in said first FIFO, when said NACK response is received by said first FIFO.

41. An interface according to claim 38, further including the step of:

disabling said NACK response packet if said NACK response packet is a second sequential NACK response packet.