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Split computer architecture

  • US 20030212755A1
  • Filed: 03/06/2003
  • Published: 11/13/2003
  • Est. Priority Date: 10/30/1998
  • Status: Active Grant
First Claim
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1. A remote-distance communications interface between a processor and physically disassociated peripheral controllers, comprising:

  • a first data bus onto which the processor communicates;

    a second data bus, physically disassociated from the first data bus, onto which the associated peripheral controllers communicate; and

    a bus interface coupling the first and second data buses to organize communication between said processor and said disassociated peripheral controllers and including at least one clock domain barrier between said first and second data buses.

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