III-V Nitride homoepitaxial material of improved MOVPE epitaxial quality (surface texture and defect density) formed on free-standing (Al,In,Ga)N substrates, and opto-electronic and electronic devices comprising same

• US 20030213964A1
• Filed: 12/06/2002
• Published: 11/20/2003
• Est. Priority Date: 03/13/2000
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Landini, Barbara E., Keogh, David M., Brandes, George R., Xu, Xueping, Vaudo, Robert P., Flynn, Jeffrey S.
• Granted Patent: US 8,212,259 B2
• Time in Patent Office: Days
• US Class Current: 257/85
• CPC Class Codes: C30B 23/00 Single-crystal growth by condensing evaporated or sublimed materials
• CPC Class Codes: C30B 25/00 Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 25/183 being provided with a buffer layer, e.g. a lattice matching layer
• CPC Class Codes: C30B 29/403 AIII-nitrides
• CPC Class Codes: C30B 29/406 Gallium nitride
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02581 Transition metal or rare earth elements
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer of improved epitaxial quality deposited on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 10⁵, nitrogen source material partial pressure in a range of from about 1 to about 10³ torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 10² microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

Claims

1. A III-V nitride homoepitaxial layer, deposited on a corresponding III-V nitride material substrate by a VPE process, using Group III source material and nitrogen source material and under deposition conditions including:

V/III ratio in a range of from about 1 to about 10⁵,

nitrogen source material partial pressure in a range of from about 1 to about 10³ torr,

growth temperature in a range of from about 500 to about 1250 degrees Celsius, and

growth rate in a range of from about 0.1 micron per hour to about 3×

10² microns per hour.

2. The III-V nitride homoepitaxial layer of claim 1, having a dislocation density of less than 1E6 dislocations per square centimeter.

3. The III-V nitride homoepitaxial layer of claim 1, having a thickness of at least 0.5 micron.

4. The III-V nitride homoepitaxial layer of claim 1, having a thickness of at least 3.0 microns.

5. The III-V nitride homoepitaxial layer of claim 1, having a thickness of at least 3.0 microns and a dislocation density of less than 1E6 dislocations per square centimeter.

6. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate is a free-standing substrate.

7. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate has a crystallographic orientation selected from the group consisting of (0001), (000{overscore (1)}), and offcuts thereof.

8. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate has a crystallographic orientation selected from the group consisting of {0001}, {1 1{overscore (2)}0}, {1{overscore (1)}00}, and offcuts therefrom.

9. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate is GaN, and wherein the homoepitaxial layer is deposited on the Ga face of the substrate.

10. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate is GaN, and wherein the homoepitaxial layer is deposited on the N face of the substrate.

11. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate is oxidized to provide a smooth deposition surface before deposition of the homoepitaxial layer thereon.

12. The III-V nitride homoepitaxial layer of claim 1, wherein an epi interlayer is applied to a deposition surface of the III-V nitride material substrate before deposition of the homoepitaxial layer thereon.

13. The III-V nitride homoepitaxial layer of claim 12, wherein the epi interlayer comprises different lattice-matched or lattice-mismatched (Al,In,Ga)N compounds.

14. The III-V nitride homoepitaxial layer of claim 1, wherein the III-V nitride material substrate is annealed before deposition of the homoepitaxial layer thereon.

15. The III-V nitride homoepitaxial layer of claim 1, wherein a surfactant is applied to a deposition surface of the III-V nitride material substrate before deposition of the homoepitaxial layer thereon, to facilitate nucleation of the homoepitaxial layer thereon.

16. The III-V nitride homoepitaxial layer of claim 1, wherein a mesa is formed in the III-V nitride material substrate before deposition of the homoepitaxial layer thereon, and wherein the homoepitaxial layer is deposited on or laterally from said mesa.

17. The III-V nitride homoepitaxial layer of claim 16, wherein said mesa is of sufficient area to enable crystallographic propagation termination and dislocation termination during deposition of the homoepitaxial layer.

18. The III-V nitride homoepitaxial layer of claim 16, wherein an area around said mesa is masked to prevent growth thereon during deposition of the homoepitaxial layer.

19. The III-V nitride homoepitaxial layer of claim 16, wherein an area around said mesa is etched for containing growth in said area during deposition of the homoepitaxial layer.

20. The III-V nitride homoepitaxial layer of claim 1, comprising GaN, and wherein the III-V nitride material substrate correspondingly comprises GaN.

21. The III-V nitride homoepitaxial layer of claim 1, comprising AlGaN, and wherein the III-V nitride material substrate correspondingly comprises AlGaN.

22. The III-V nitride homoepitaxial layer of claim 1, comprising AlInGaN, and wherein the III-V nitride material substrate correspondingly comprises AlInGaN.

23. The III-V nitride homoepitaxial layer of claim 1, doped n-type, p-type, or semi-insulating.

24. The III-V nitride homoepitaxial layer of claim 1, wherein the homoepitaxial layer and the substrate have a sheet resistance greater than 1E5 ohms per square centimeter.

25. The III-V nitride homoepitaxial layer of claim 1, wherein the homoepitaxial layer and the substrate have a sheet resistance greater than 1E4 ohms per square centimeter.

26. A homoepitaxial III-V nitride article, comprising a III-V nitride homoepitaxial layer deposited on a free-standing III-V nitride material substrate, wherein said III-V nitride homoepitaxial layer has a dislocation density of less than 1E6 dislocations per square centimeter.

27. The homoepitaxial III-V nitride article of claim 26, wherein said III-V nitride homoepitaxial layer has a thickness of at least 0.5 micron.

28. The homoepitaxial III-V nitride article of claim 26, wherein said III-V nitride homoepitaxial layer has a thickness of at least 3.0 microns.

29. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate comprises a (Al,Ga,In)N boule.

30. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a diameter of greater than 1 cm.

31. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a diameter of greater than 2.5 cm.

32. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a diameter of greater than 7.5 cm.

33. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a length of greater than 1 mm.

34. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a length of greater than 0.5 cm.

35. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a length of greater than 1 cm.

36. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a top surface defect density of less than 10⁷ defects per square centimeter.

37. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a top surface defect density of less than 10⁶ defects per square centimeter.

38. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a top surface defect density of less than 10⁴ defects per square centimeter.

39. The homoepitaxial III-V nitride article of claim 29, wherein the (Al,Ga,In)N boule has a top surface defect density of less than 10⁵ defects per square centimeter, a diameter of at least 5 cm, and a thickness of at least 1 cm.

40. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate has a crystallographic orientation selected from the group consisting of (0001), (000{overscore (1)}), and offcuts thereof.

41. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate has a crystallographic orientation selected from the group consisting of {0001}, {11{overscore (2)}0}, {1{overscore (1)}00}, and offcuts therefrom.

42. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate is GaN, and wherein the homoepitaxial layer is deposited on the Ga face of the substrate.

43. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate is GaN, and wherein the homoepitaxial layer is deposited on the N face of the substrate.

44. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate is oxidized to provide a smooth deposition surface before deposition of the homoepitaxial layer thereon.

45. The homoepitaxial III-V nitride article of claim 26, wherein an epi interlayer is applied to a deposition surface of said free-standing III-V nitride material substrate before deposition of the homoepitaxial layer thereon.

46. The homoepitaxial III-V nitride article of claim 45, wherein the epi interlayer comprises different lattice-matched or lattice-mismatched (Al,In,Ga)N compounds.

47. The homoepitaxial III-V nitride article of claim 26, wherein said free-standing III-V nitride material substrate is annealed before deposition of the homoepitaxial layer thereon.

48. The homoepitaxial III-V nitride article of claim 26, wherein a surfactant is applied to a deposition surface of said free-standing III-V nitride material substrate before deposition of the homoepitaxial layer thereon, to facilitate nucleation of the homoepitaxial layer thereon.

49. The homoepitaxial III-V nitride article of claim 26, wherein a mesa is formed in said free-standing III-V nitride material substrate before deposition of the homoepitaxial layer thereon, and wherein the homoepitaxial layer is deposited on or laterally from said mesa.

50. The homoepitaxial III-V nitride article of claim 49, wherein said mesa is of sufficient area to enable crystallographic propagation termination and dislocation termination during deposition of the homoepitaxial layer.

51. The homoepitaxial III-V nitride article of claim 49, wherein an area around said mesa is masked to prevent growth thereon during deposition of the homoepitaxial layer.

52. The homoepitaxial III-V nitride article of claim 49, wherein an area around said mesa is etched for containing growth in said area during deposition of the homoepitaxial layer.

53. The homoepitaxial III-V nitride article of claim 26, wherein the III-V nitride homoepitaxial layer and the free-standing III-V nitride material substrate both comprise GaN.

54. The homoepitaxial III-V nitride article of claim 26, wherein the III-V nitride homoepitaxial layer and the free-standing III-V nitride material substrate both comprise AlGaN.

55. The homoepitaxial III-V nitride article of claim 26, wherein the III-V nitride homoepitaxial layer and the free-standing III-V nitride material substrate both comprise AlInGaN.

56. The homoepitaxial III-V nitride article of claim 26, wherein the III-V nitride homoepitaxial layer is doped n-type, p-type, or semi-insulating.

57. The homoepitaxial III-V nitride article of claim 26, wherein the III-V nitride homoepitaxial layer and the free-standing III-V nitride material substrate have a sheet resistance greater than 1E5 ohms per square centimeter.

58. The homoepitaxial III-V nitride article of claim 26, wherein the III-V nitride homoepitaxial layer and the free-standing III-V nitride material substrate have a sheet resistance greater than 1E4 ohms per square centimeter

59. The homoepitaxial III-V nitride article of claim 26, free of contamination at an interface between said homoepitaxial layer and said substrate.

60. A III-V nitride homoepitaxial microelectronic device structure, comprising a III-V nitride homoepitaxial epi layer deposited on a FS III-V nitride material substrate.2

61. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the III-V nitride homoepitaxial epi layer comprises non-(0001) homoepitaxial step flow crystal growth.

62. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the III-V nitride homoepitaxial epi layer has a <

11 {overscore (2 )}0>

offcut direction.

63. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the III-V nitride homoepitaxial epi layer has a <

10 {overscore (1 )}0>

offcut direction.

64. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the III-V nitride homoepitaxial epi layer has an offcut direction between <

11 {overscore (2 )}0> and

<

10 {overscore (1 )}0>

.

65. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the substrate is finished.

66. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the substrate is unfinished.

67. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the III-V nitride homoepitaxial epi layer comprises a lattice-matched AlInGaN epi layer.

68. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein the substrate comprises FS GaN with a graded AlGaN layer thereon.

69. The III-V nitride homoepitaxial microelectronic device structure of claim 60, having a dislocation density of less than 5E8 dislocations per square centimeter.

70. The III-V nitride homoepitaxial microelectronic device structure of claim 60, having a dislocation density of less than 5E7 dislocations per square centimeter.

71. The III-V nitride homoepitaxial microelectronic device structure of claim 60, having a dislocation density of less than 5E6 dislocations per square centimeter.

72. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein said substrate comprises GaN, and the III-V nitride homoepitaxial epi layer is deposited on a Ga face of said substrate.

73. The III-V nitride homoepitaxial microelectronic device structure of claim 60, wherein said substrate comprises GaN, and the III-V nitride homoepitaxial epi layer is deposited on a N face of the substrate.

74. A microelectronic device comprising a III-V nitride homoepitaxial microelectronic device structure as in claim 60.

75. The microelectronic device of claim 74, comprising a UV LED.

76. The microelectronic device of claim 74, comprising an AlGaN/GaN high electron mobility transistors (HEMT).

77. The microelectronic device of claim 74, comprising a laser diode.

78. A system comprising the microelectronic device of claim 74.

79. An epitaxial growth reactor comprising a susceptor with a CTE-matched coating thereon to prolong operating life of the susceptor.