Multichip wafer-level package and method for manufacturing the same

• US 20030214029A1
• Filed: 03/21/2003
• Published: 11/20/2003
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chen, Chih Lung, Yee, Kuo Chung, Tao, Su, Liau, Hsing Jung, Kao, Jen Chieh
• Granted Patent: US 6,768,207 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/10 : characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/07811 : Extrinsic, i.e. with electrical conductive fillers
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A multichip wafer-level package comprises a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding pad ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding pad ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding pad ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding pad ring corresponding to the first bonding pad ring of the first chip. The bump ring is disposed between the first bonding pad ring of the first chip and the second bonding pad ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating the semiconductor device. The bumps electrically connect the internal bonding pads of the first chip to the bonding pads of the second chip.

Claims

1. A multichip wafer-level package comprising:

a first chip having a semiconductor device, a first bonding pad ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding pad ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding pad ring and electrically connected to the semiconductor device for electrically connecting to an external circuit;

a second chip having an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding pad ring corresponding to the first bonding pad ring of the first chip;

a bump ring disposed between the first bonding pad ring of the first chip and the second bonding pad ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating the semiconductor device; and

a plurality of bumps electrically connecting the internal bonding pads of the first chip to the bonding pads of the second chip.

2. The multichip wafer-level package according to claim 1, wherein the first bonding pad ring of the first chip and the second bonding pad ring of the second chip are aluminum bonding pad rings.

3. The multichip wafer-level package according to claim 1, wherein the bump ring and the bumps are anisotropic conductive adhesive film (ACF).

4. The multichip wafer-level package according to claim 1, wherein the bump ring and the bumps are solders.

5. The multichip wafer-level package according to claim 1, wherein the respective bonding pad rings of the first chip and the second chip further have an under bump metallurgy (UBM).

6. The multichip wafer-level package according to claim 1, wherein the bump ring is a gold bump ring such that the cavity can be a hermetical cavity.

7. The multichip wafer-level package according to claim 1, wherein the material of the first chip and the second chip is silicon.

8. The multichip wafer-level package according to claim 1, wherein the semiconductor device is selected from a set of integrated circuit, micro-electro mechanical system (MEMs) component, moving part, and sensor.

9. The multichip wafer-level package according to claim 1, wherein the electronic device is an integrated circuit.

10. A method for manufacturing multichip wafer-level package with a hermetical cavity, comprising following steps:

providing a first wafer comprising a plurality of first chips wherein each first chip is spaced to one another by scribe lines and each chip has a semiconductor device, a bonding pad ring, a plurality of internal bonding pads disposed within the bonding pad ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding pad ring and electrically connected to the semiconductor device;

providing a second wafer comprising a plurality of second chips wherein each second chip is spaced to one another by scribe lines and each chip has a plurality of electronic devices, a plurality of bonding pads electrically connected to the electronic devices and corresponding to the internal bonding pads of the first chip, and a second bonding pad ring corresponding to the first bonding pad ring of the first chip;

forming a adhesion ring on the bonding pad ring of the first chip or the bonding pad ring of the second chip;

forming conductive bumps on the internal bonding pads of the first chip or bonding pads of the second chip;

aligning the first wafer with the second wafer and then bonding them together such that the adhesion ring connects the bonding pad ring of the first chip and the bonding pad ring of the second chip so as to form a hermetical cavity between the first chip and the second chip and such that the conductive bumps electrically connect the internal bonding pads of the first chip and the bonding pads of the second chip; and

cutting the first wafer and the second wafer along the scribe lines of the first wafer and the second wafer respectively so as to form packages individually.

11. The method according to claim 10, wherein the steps of forming a adhesion ring and forming conductive bumps further comprise following steps:

forming UBMs on the bonding pad ring and on the internal bonding pads of the first chip;

forming UBMs on the bonding pad ring and on the bonding pads of the second chip;

forming a gold bump ring on the bonding pad ring of the first chip or on the bonding pad ring of the second chip; and

forming a plurality of bumps on the internal bonding pads of the first chip or the bonding pads of the second chip.

12. The method according to claim 11, wherein the each UBM of the first substrate and the second substrate comprises an adhesion layer, a barrier layer, and a wetting layer.

13. The method according to claim 11, wherein the adhesion ring and the conductive bumps are anisotropic conductive adhesive film (ACF).

14. The method according to claim 11, wherein the adhesion ring and the conductive bumps are solders.

15. The method according to claim 10, wherein the first wafer and the second wafer are selected from a set of organic substrate, bismaleimide-triazine (BT) substrate, and glass substrate.

16. The method according to claim 10, wherein the material of the first wafer and the second wafer is silicon.

17. The method according to claim 10, wherein the semiconductor device is selected from a set of integrated circuit, micro-electro mechanical system (MEMs) component, moving part, and sensor.

18. The method according to claim 10, wherein the electronic device is an integrated circuit.