Early triggered ESD MOSFET protection circuit and method thereof

• US 20030214768A1
• Filed: 09/27/2002
• Published: 11/20/2003
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Lin, Shi-Tron, Chen, Wei-Fan, Lien, Chen-Hsin
• Granted Patent: US 6,958,896 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0274 involving a parasitic bipolar transistor triggered by the electrical biasing of the gate electrode of the field effect transistor, e.g. gate coupled transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 Å and less.

Claims

1. An MOSFET ESD protection circuit coupled between a first and a second node, the circuit comprising:

a first transistor having a drain coupled to the first node and a source coupled to the second node, and

an ESD-transient negative voltage generator receiving the ESD voltage and outputting an ESD-transient negative voltage to a gate of the first transistor to reduce a triggering voltage for the first transistor during an ESD event.

2. The circuit as claimed in claim 1 further comprising a rectifier receiving and rectifying the ESD-transient negative voltage, and outputting the rectified ESD-transient negative voltage to the gate of the first transistor.

3. The circuit as claimed in claim 1, wherein the ESD-transient negative voltage generator comprises:

a transient oscillation circuit receiving the ESD voltage and generating an oscillation signal when the ESD voltage is applied to the first node; and

a first capacitor having one end coupled to receive the oscillation signal and the other end coupled to the gate of the first transistor.

4. The circuit as claimed in claim 3 further comprising a second transistor having a drain and gate commonly coupled to the gate of the first transistor, and a source coupled to the second node.

5. The circuit as claimed in claim 3, wherein the transient oscillation circuit comprises:

an inverting gate having at least one inverting logic gate; and

a plurality of inverters connected in series, having a first inverter with an input coupled to an output of the inverting gate and a last inverter with an output coupled to a first input of the inverting gate.

6. The circuit as claimed in claim 5 further comprising:

a second capacitor coupled to the second input of the inverting gate; and

a second resistor coupled to a second input of the inverting gate.

7. The circuit as claimed in claim 6, wherein the inverting gate is a NOR gate and the second resistor is coupled to the first node.

8. The circuit as claimed in claim 6, wherein the inverting gate is a NAND gate and the second resistor is coupled to the second node.

9. The circuit as claimed in claim 1 further comprising a third transistor having a drain and gate commonly coupled to the gate of the first transistor, and a source coupled to the second node.

10. The circuit as claimed in claim 1 further comprising at least a diode coupled between the gate of the first transistor and the second node.

11. The circuit as claimed in claim 10 further comprising a plurality of diodes serially coupled between the gate of the first transistor and the second node.

12. The circuit as claimed in claim 1 further comprising a switch connected between the gate of the first transistor and the second node.

13. The circuit as claimed in claim 1, wherein the first node is a pad.

14. The circuit as claimed in claim 1, wherein the first node is a VDD power bus.

15. The circuit as claimed in claim 1, wherein the first node is a VSS power bus.

16. The circuit as claimed in claim 1, wherein the first transistor has a gate oxide layer with a thickness less than 75 Å

.

17. The circuit as claimed in claim 1, wherein the first transistor has a gate oxide layer with a thickness less than 45 Å

.

18. The circuit as claimed in claim 1, wherein the first transistor has a gate oxide layer with a thickness smaller than 25 Å

.

19. A method for early triggering of an ESD protection circuit for an integrated circuit, the ESD protection circuit having a MOS transistor with a drain coupled to a first node and a source coupled to a second node, the method comprising the step of:

receiving an ESD voltage and outputting an ESD-transient negative voltage to a gate of the MOS transistor to reduce a triggering voltage for the MOS transistor to enter snapback when the ESD voltage is applied to the first node.

20. The method as claimed in claim 19 further comprising the step of:

turning off the MOS transistor during normal operation of the integrated circuit.

21. The method as claimed in claim 19 further comprising the step of:

generating an oscillation signal based on the ESD voltage to provide the ESD-transient negative voltage.