Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device

• US 20030214841A9
• Filed: 11/27/2002
• Published: 11/20/2003
• Est. Priority Date: 04/28/2000
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Crowley, Matthew P.
• Granted Patent: US 6,856,572 B2
• Time in Patent Office: Days
• US Class Current: 365/185.03
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A memory array decoder organization readily interfaces to array lines having extremely dense pitch, and in particular interfaces to extremely dense array lines of a three-dimensional memory array. In an exemplary embodiment, a multi-headed decoder includes a group of array line driver circuits associated with a single decode node. Each array line driver circuit couples its associated array line through a first device to an associated upper bias node which is generated to convey either a selected bias condition or an unselected bias condition thereon appropriate for the array line. Each array line driver circuit also couples its associated array line through a second device to an associated lower bias node which is generated to convey an unselected bias condition appropriate for the array line. The array line driver circuits for several different decode nodes may be physically arranged in one or more banks.

Claims

1. An integrated circuit comprising:

a memory array having at least a plurality of array lines on a first layer of the memory array;

a decoder circuit for generating a plurality of decoder outputs;

a plurality of array line driver circuits, each responsive to an associated decoder output and having an output coupled to a corresponding one of the plurality of array lines, each respective array line driver circuit comprising

a first device for driving the respective array line at times to a selected array line bias condition and at other times to an unselected array line bias condition; and

a second device for driving the respective array line at times to the unselected array line bias condition.

2. The integrated circuit as recited in claim 1 wherein each respective first device is configured to couple the respective array line to an associated bias node which is driven at times to the unselected array line bias condition and at other times to a selected array line bias condition.

3. The integrated circuit as recited in claim 1 wherein:

the memory array comprises a three-dimensional memory array having a plurality of array lines of a first type on each of at least two layers.

4. The integrated circuit as recited in claim 3 wherein:

the plurality of array lines of the first type comprise word lines for the array.

5. The integrated circuit as recited in claim 3 wherein:

the plurality of array lines of the first type comprises bit lines for the array.

6. The integrated circuit as recited in claim 1 wherein:

the unselected bias condition at times comprises an unselected bias voltage; and

the unselected bias condition at other times comprises a floating state.

7. The integrated circuit as recited in claim 1 further comprising:

a first bias generator circuit for generating on a first bias node at times the selected array line bias condition and at other times the unselected array line bias condition;

wherein the respective first device of at least two array line driver circuits is coupled to the first bias node.

8. The integrated circuit as recited in claim 7 further comprising:

a second bias generator circuit for generating on a second bias node at times the unselected array line bias condition;

wherein the respective second device of at least two array line driver circuits is coupled to the second bias node.

9. The integrated circuit as recited in claim 1 further comprising:

a first bias generator circuit for generating on a first bias node at times the unselected array line bias condition; and

a second bias generator circuit for generating on a second bias node at times the unselected array line bias condition;

wherein the respective first device of at least two array line driver circuits is coupled to the first bias node; and

wherein the respective second device of at least two array line driver circuits is coupled to the second bias node.

10. The integrated circuit as recited in claim 6 wherein:

the first device of each array line driver circuits comprises a PMOS transistor having a threshold voltage lower in magnitude than the unselected bias voltage.

11. An integrated circuit comprising:

a memory array having array lines on at least one layer exiting to a given side of the array;

a decoder circuit for generating a plurality of decoder outputs;

a plurality of array line driver circuits, each having an output coupled to a corresponding one of the array lines, a respective plurality of said array line driver circuits coupled to each respective decoder output, each array line driver circuit for coupling its corresponding array line to an associated one of a plurality of first bias nodes when its associated decoder output is selected, and for coupling its corresponding array line to an associated one of a plurality of second bias nodes when its associated decoder output is unselected;

a plurality of first bias circuits for respectively generating a suitable condition on the plurality of first bias nodes; and

a plurality of second bias circuits for respectively generating a suitable condition on the plurality of second bias nodes.

12. The integrated circuit as recited in claim 11 wherein:

the suitable condition on at least one of the first bias nodes is at times a selected array line bias condition, whereby an array line driver coupled thereto and driven by a selected decode node couples its associated array line to the selected array line bias condition; and

the suitable condition on at least another one of the first bias nodes is at times an unselected array line bias condition, whereby an array line driver coupled thereto and driven by a selected decode node couples its associated array line to the unselected array line bias condition.

13. The integrated circuit as recited in claim 12 wherein the suitable condition on at least one of the first bias nodes is at times a floating node condition, whereby an array line driver coupled thereto and driven by a selected decode node couples its associated array line to a floating node.

14. The integrated circuit as recited in claim 11 wherein:

the number of first bias circuits and thereby the number of first bias nodes is equal to the number of array line drivers coupled to the same decode node.

15. The integrated circuit as recited in claim 11 wherein:

the memory array comprises array lines on each of at least two layers exiting to the given side of the array.

16. The integrated circuit as recited in claim 15 wherein:

the number of second bias circuits and thereby the number of second bias nodes is equal to the number of layers having array lines exiting to the given side of the memory array.

17. The integrated circuit as recited in claim 15 wherein:

the number of second bias circuits and thereby the number of second bias nodes is less than the number of layers having array lines exiting to the given side of the memory array.

18. An integrated circuit comprising:

a three-dimensional memory array having array lines of a first type on at least one layer;

a plurality M of upper bias node circuits for respectively generating a suitable condition on a plurality M of upper bias nodes;

a plurality N of lower bias node circuits for respectively generating on a plurality N of lower bias nodes a bias condition appropriate for unselected array lines on an associated layer;

a decoder circuit comprising a plurality of decoder outputs;

a plurality of array line driver circuits, each having an input coupled to an associated decoder output, and having an output coupled to a corresponding one of the array lines, wherein a respective plurality M of said array line driver circuits is associated with each respective decoder output, and wherein each respective array line driver circuit associated with a given decode node couples its corresponding array line at times to a respective one of the plurality M of upper bias nodes, and couples its corresponding array line at other times to an associated one of the plurality N of lower bias nodes.

19. The integrated circuit as recited in claim 18 wherein:

each respective array line driver circuit associated with a given decode node couples its corresponding array line through a respective first device to a respective one of the plurality M of upper bias nodes when the given decode node is selected, and couples its corresponding array line through a respective second device to an associated one of the plurality N of lower bias nodes when the given decode node is unselected.

20. The integrated circuit as recited in claim 18 wherein:

M is equal to N.

21. The integrated circuit as recited in claim 18 wherein:

M is greater than N.

22. The integrated circuit as recited in claim 18 wherein:

the memory array has array lines of a first type on each of a number of layers which is greater than N.

23. The integrated circuit as recited in claim 18 wherein:

the memory array has array lines of a first type on each of a number of layers which is equal to N or N+1.

24. The integrated circuit as recited in claim 18 wherein:

M is equal to 16;

N is equal to 4; and

the array has 8 memory planes.

25. The integrated circuit as recited in claim 24 wherein:

the memory array has array lines of the first type on 5 layers, each respective one on the lower-most layer being connected to a respective one on the upper-most layer and driven respectively as one logical array line.

26. The integrated circuit as recited in claim 24 wherein:

the memory array has array lines of the first type on 4 layers.

27. The integrated circuit as recited in claim 18 wherein:

the memory array has array lines of the first type on at least 4 layers, and array lines of a first pair of layers share a first one of the N lower bias nodes, and array lines of a second pair of layers share a second one of the N lower bias nodes.

28. An integrated circuit comprising:

a three-dimensional memory array having array lines of a first type on each of at least two layers;

a decoder circuit comprising a plurality of decoder outputs;

a plurality of array line driver circuits, each having an input coupled to an associated decoder output, and having an output coupled to a corresponding one of the array lines, wherein a respective plurality M of said array line driver circuits is associated with each respective decoder output;

wherein each respective array line driver circuit associated with a given decode node couples its corresponding array line to a respective one of a plurality M of selected bias nodes when its associated decode node is selected, and couples its corresponding array line to an associated one of a plurality N of unselected bias nodes when its associated decode node is not selected;

wherein the array line driver circuits associated with a given decode node correspond to at least two array lines on each of at least two layers of the memory array;

a plurality M of selected bias circuits for respectively generating a suitable condition on the plurality M of selected bias nodes; and

a plurality N of unselected bias circuits for respectively generating on the plurality N of unselected bias nodes a bias condition appropriate for unselected array lines on an associated one of the layers.

29. The integrated circuit as recited in claim 28 wherein:

at most one of the selected bias circuits conveys a selected bias voltage onto its associated selected bias node, and remaining ones of the selected bias circuits convey an unselected bias condition on the remaining selected bias nodes.

30. The integrated circuit as recited in claim 29 wherein:

the unselected bias condition includes an unselected bias voltage for those selected bias nodes associated with unselected array lines on a selected layer of the array.

31. The integrated circuit as recited in claim 29 wherein:

the unselected bias condition includes an unselected bias voltage for those selected bias nodes associated with array lines on a non-selected layer of the array adjacent to the selected layer.

32. The integrated circuit as recited in claim 29 wherein:

the unselected bias condition includes a floating condition for those selected bias nodes associated with array lines on a layers of the array other than the selected layer and layers adjacent to the selected layer.

33. The integrated circuit as recited in claim 28 wherein:

M is equal to N.

34. The integrated circuit as recited in claim 28 wherein:

M is greater than N.

35. The integrated circuit as recited in claim 28 wherein:

the memory array has array lines of a first type on each of a number of layers which is greater than N.

36. The integrated circuit as recited in claim 28 wherein:

the memory array has array lines of a first type on each of a number of layers which is equal to N or N+1.

37. The integrated circuit as recited in claim 28 wherein:

M is equal to 16;

N is equal to 4; and

the array has 8 memory planes.

38. The integrated circuit as recited in claim 37 wherein:

the memory array has array lines of the first type on 5 layers, each respective one on the lower-most layer being connected to a respective one on the upper-most layer and driven respectively as one logical array line.

39. The integrated circuit as recited in claim 37 wherein:

the memory array has array lines of the first type on 4 layers.

40. The integrated circuit as recited in claim 28 wherein:

the memory array has array lines of the first type on at least 4 layers, and array lines of a first pair of layers share a first one of the N lower bias nodes, and array lines of a second pair of layers share a second one of the N lower bias nodes.

41. An integrated circuit comprising:

a memory array having word lines and bit lines;

a decoder circuit comprising a plurality of decoder outputs;

a respective word line driver circuit for each respective word line, each word line driver circuit responsive to an associated decoder output and having a first device for driving its associated word line to either a selected bias voltage or to an unselected bias condition conveyed on a first bus line, and having a second device for driving its associated word line to an unselected bias condition conveyed on a second bus line.

42. The integrated circuit as recited in claim 41 wherein:

the memory array comprises a three-dimensional memory array having word lines on at least two layers of the memory array.

43. The integrated circuit as recited in claim 42 wherein:

each decoder output is associated with a respective plurality of word line driver circuits, each having word line driver circuits respectively associated with at least two word lines on each of at least two layers of the memory array.

44. The integrated circuit as recited in claim 41 wherein:

the unselected bias condition at times comprises an unselected bias voltage; and

the unselected bias condition at other times comprises a floating state.

45. The integrated circuit as recited in claim 41 further comprising:

a plurality of first bias generator circuits for generating on a respective plurality of first bus lines at times the selected bias voltage and at other times the unselected bias condition; and

a plurality of second bias generator circuits for generating on a respective plurality of second bus lines at times the unselected bias condition;

wherein the respective first device of at least two word line driver circuits is coupled to one of the first bus lines; and

wherein the respective second device of at least two word line driver circuits is coupled to one of the second bus lines.

46. The integrated circuit as recited in claim 44 wherein:

the first device of each word line driver circuit comprises a PMOS transistor having a threshold voltage lower in magnitude than the unselected bias voltage.