Data access arrangement using a high frequency transformer for electrical isolation

• US 20030215020A1
• Filed: 05/14/2002
• Published: 11/20/2003
• Est. Priority Date: 05/14/2002
• Status: Active Grant

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Cookman, Jordan C., Dong, Ping
• Granted Patent: US 7,277,491 B2
• Time in Patent Office: Days
• US Class Current: 375/258
• CPC Class Codes: H01F 2019/085 Transformer for galvanic isolation
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation

Abstract

An electrical isolation barrier for use in a Data Access Arrangement uses a high frequency (HF) transformer 24 to provide isolation. An input signal, which may be analog or digital, is connected to a modulator. The analog output of the modulator is connected to the input of the HF transformer. The output of the HF transformer is connected to the input of a demodulator. Simple amplitude modulation can be used in the modulator to modulate the input signal to the frequency range of operation of the HF transformer. A simple low pass filter may be incorporated in the demodulator to remove harmonic distortion caused by the HF transformer. The output signal of the demodulator is substantially the same as input signal.

Claims

1. An electrical isolation barrier for use in a data access arrangement, comprising, in combination:

An input circuit and an output circuit;

An HF transformer for providing electrical isolation between the input circuit and the output circuit and having a frequency range of desired operation, said transformer having two ports;

A modulator having an input and an output,

said modulator input capable of being connected to the input circuit, said modulator modulating the input signal to frequencies within the frequency range of the transformer;

said modulator output connected to the first port of the transformer to supply the modulated signals to the transformer;

A demodulator having an input and an output,

said demodulator input connected to the second port of the transformer, said demodulator demodulating signals from the frequency range of the transformer to an output signal for use by the output circuit.

2. The electrical isolation barrier of claim 1 wherein:

the modulator includes a multiplier, said multiplier being connected to a clock for multiplying the input signal by a clock signal;

the demodulator includes a multiplier, said multiplier connected to a clock for multiplying the output of the transformer by said clock signal; and

the demodulator includes a low pass filter to remove distortion from the recovered signal.

3. The electrical isolation barrier of claim 1 wherein:

the input signal to the modulator is a first 1-bit digital signal;

the modulator converts said first 1-bit digital signal to an analog input signal having frequencies in the frequency range of the transformer;

the demodulator converts signals having frequencies in the frequency range of the transformer to recover the first 1-bit digital signal.

4. The electrical isolation barrier of claim 1 further including a multiplexor to multiplex status or control signals with line signals for transmission over the electrical isolation barrier.

5. The electrical isolation barrier of claim 4 wherein the signal output from the demodulator includes status or control information.

6. The electrical isolation barrier of claim 3 wherein at least some portion of the first 1-bit digital signal is generated using sigma-delta techniques.

7. The electrical isolation barrier of claim 3 wherein the input circuit includes a multiplexor to multiplex digital status or control signals with a second 1-bit digital signal to form the first 1-bit digital signal.

8. The electrical isolation barrier of claim 7 wherein the output circuit includes a demultiplexor to extract digital status or control signals and the second 1-bit digital signal from the first 1-bit digital signal.

9. The electrical isolation barrier of claim 8 wherein the second 1-bit digital signal is generated using sigma-delta techniques.

10. The electrical isolation barrier of claim 8 wherein the multiplexor includes a frame generation circuit to align the digital status or control signals.

11. The electrical isolation barrier of claim 8 wherein the demultiplexor includes a frame detection circuit to detect the alignment of the digital status or control signals.

48. The electrical isolation barrier of claim 4 wherein said status signals are of different frequencies from said control signals.

12. The method of providing an electrical isolation barrier in a modem system comprising the steps of:

providing a high frequency transformer in the data access arrangement section of the modem, which transformer has a predetermined frequency operation range and an input port and an output port;

modulating an input signal to the frequency operation range of the transformer and providing the modulated first signal to the transformer input port;

obtaining from the output port of the transformer an output signal, and

demodulating the output signal to recover the input signal.

13. The method of claim 12 wherein

the input signal is a 1-bit digital signal;

and

the step of modulating the input signal includes multiplying an analog clock signal with the 1-bit digital signal to form a high-frequency analog signal; and

the step of demodulating the output signal to recover the input signal includes demodulating the high frequency signal by analog clock multiplication.

14. The method of claim 13 wherein at least some of the bits in the 1-bit digital signal are obtained using sigma-delta techniques.

15. An electrical isolation barrier for use in a data access arrangement for providing electrical isolation between a line side circuit and a system side circuit, comprising, in combination:

a first pair of input and output circuits for a TX signal and a second pair of input and output circuits for an RX signal, wherein the first input circuit and the second output circuit are located in the line side circuit, and the second input circuit and the first output circuit are located in the system side circuit;

a first HF transformer for providing electrical isolation between the first pair of input and output circuits and having a frequency range of desired operation, said first transformer having two ports;

a first modulator having an input and an output,

said first modulator input capable of being connected to the input circuit of the first pair of input and output circuits and modulating an input signal to frequencies within the frequency range of the first transformer;

said first modulator output connected to the first port of the first transformer to supply the modulated signals to the first transformer;

a first demodulator having an input and an output,

said first demodulator input connected to the second port of the first transformer for demodulating signals from the frequency range of the first transformer to an output signal for use by the output circuit of the first pair of input and output circuits;

whereby the harmonics of the RX signal passing through the first transformer fall outside of the frequency range of the modulated signal;

a second HF transformer for providing electrical isolation between the second pair of input and output circuits and having a frequency range of desired operation, said second transformer having two ports;

a second modulator having an input and an output,

said second modulator input capable of being connected to the input circuit of the second pair of input and output circuits and modulating the input signal to frequencies within the frequency range of the second transformer;

said second modulator output connected to the first port of the second transformer to supply the modulated signals to the second transformer;

a second demodulator having an input and an output,

said second demodulator input connected to the second port of the second transformer for demodulating signals from the frequency range of the second transformer to an output signal for use by the output circuit of the second pair of input and output circuits;

whereby the harmonics of the TX signal passing through the second transformer fall outside of the frequency range of the modulated signal.

16. An electrical isolation barrier for use in a data access arrangement for providing electrical isolation between a system side circuit and a line side circuit, comprising, in combination:

an HF transformer having a desired frequency range of operation, and having a first port and a second port;

a first modulator coupled to the first port of said transformer, said first modulator modulating a first base band signal to a first analog pass band signal within said desired frequency range and transmitting the modulated signal to said transformer;

a first demodulator coupled to said second port of said transformer, said demodulator demodulating said first pass band signal to recover said first base band signal for transmission to said line side circuit.

17. The electrical isolation barrier of claim 16 wherein said first modulator is coupled to said transformer through a first HF hybrid circuit and said transformer is coupled to said first demodulator through a second HF hybrid circuit.

18. The electrical isolation barrier of claim 16, wherein the system side circuit includes (1) a codec for converting digital modem signals to an analog transmit signal, and (2) a first multiplexor connected to said first modulator, said first multiplexor receiving analog control signals and said analog transmit signal and multiplexing said analog control signals and said analog transmit signal to form said first base band signal.

19. The electrical isolation barrier of claim 17 including a clock recovery circuit connected to said second HF hybrid circuit for locking the frequency of said first demodulator to that of said first modulator.

20. The electrical isolation barrier of claim 18 wherein the line side circuit includes a first demultiplexor connected to first demodulator, said demodulator shifting the frequency of said first pass band signal back to the original base band and said first demultiplexor separating the said analog control signals from the said analog transmit signal.

21. The electrical isolation barrier of claim 16 wherein the line side circuit includes a LF hybrid circuit coupled to a communications line for receiving analog receive signals and transmitting analog transmit signals.

22. The electrical isolation barrier of claim 17 including

a second modulator coupled to said second port of said transformer through said second HF hybrid circuit, said second modulator modulating a second base band signal to a second analog pass band signal within said desired frequency range and transmitting it to said transformer;

a second demodulator coupled to said first port of said transformer through said first HF hybrid circuit, said second demodulator demodulating said second pass band signal to recover said second base band signal for transmission to said system side circuit.

23. The electrical isolation barrier of claim 22, wherein the line side circuit includes a second multiplexor connected to said second modulator, receiving analog status signals and an analog receive signal, said multiplexor combining said analog status signals and said analog receive signal to form said second base band signal.

24. The electrical isolation barrier of claim 23 wherein the system side circuit includes (1) a codec for converting an analog receive signal to digital modem signals and (2) a second demultiplexor connected to second demodulator, said demodulator shifting the frequency of said second analog pass band signal back to the original base band and said second demultiplexor separating said analog status signals from said analog receive signal.

25. An electrical isolation barrier for use in a data access arrangement for providing electrical isolation between a system side circuit and a line side circuit, comprising, in combination:

an HF transformer having a desired frequency range of operation, and having a first port and a second port;

a first modulator coupled to first port of said transformer, said first modulator modulating a first 1-bit digital signal to a first analog pass band signal within said desired frequency range and transmitting the modulated signal to said transformer;

a first demodulator coupled to said second port of said transformer, said demodulator demodulating said first pass band signal to recover said first 1-bit digital signal for transmission to said line side circuit.

26. The electrical isolation barrier of claim 25 wherein said first modulator is coupled to said transformer through a first HF hybrid circuit and said transformer is coupled to said first demodulator through a second HF hybrid circuit.

27. The electrical isolation barrier of claim 25, wherein the system side circuit includes (1) a digital portion of a sigma-delta codec for converting digital modem signals to a second 1-bit digital signal, and (2) a first multiplexor connected to said first modulator, said first multiplexor receiving digital control signals and said second 1-bit digital signal and multiplexing said digital control signals and second 1-bit digital signal to form said first 1-bit digital signal.

28. The electrical isolation barrier of claim 27 wherein the first multiplexor includes a first frame generation circuit to align the digital control signals.

29. The electrical isolation barrier of claim 26 including a clock recovery circuit connected to said second HF hybrid circuit for locking the frequency of said first demodulator to that of said first modulator.

30. The electrical isolation barrier of claim 27 wherein the line-side circuit includes a first demultiplexor connected to the first demodulator, said first demultiplexor separating the digital control signals and second 1-bit digital signal from the recovered first 1-bit digital signal.

31. The electrical isolation barrier of claim 30 wherein the first demultiplexor includes a frame detection circuit to detect the alignment of the digital control signals.

32. The electrical isolation barrier of claim 30, wherein the line side circuit includes an analog portion of a sigma-delta codec coupled to said first demodulator, said analog portion of sigma-delta codec converting the recovered second 1-bit digital signal into an analog transmit signal.

33. The electrical isolation barrier of claim 25 wherein the line side circuit includes a LF hybrid circuit coupled to a communications line for receiving analog receive signals and transmitting analog transmit signals.

34. The electrical isolation barrier of claim 26 including

a second modulator coupled to said second port of said transformer through said second HF hybrid circuit, said second modulator modulating a third 1-bit digital signal to a second analog pass band signal within said desired frequency range and transmitting it to said transformer;

a second demodulator coupled to said first port of said transformer through said first HF hybrid circuit, said second demodulator demodulating said second pass band signal to recover said third 1-bit digital signal for transmission to said system side circuit.

35. The electrical isolation barrier of claim 34, wherein the line side circuit includes an analog portion of a sigma-delta codec, said analog portion converting an analog receive signal to a fourth 1-bit digital signal.

36. The electrical isolation barrier of claim 35, wherein the line side circuit includes a second multiplexor connected to said second modulator, receiving digital status signals and said fourth 1-bit digital signal, said multiplexor combining said digital status signals and said fourth 1-bit digital signal to form said third 1-bit digital signal.

37. The electrical isolation barrier of claim 36 wherein the second multiplexor includes a second frame generation circuit to align the digital status signals.

38. The electrical isolation barrier of claim 36 wherein the system side circuit includes (1) a second demultiplexor connected to a second demodulator, said second demultiplexor recovering said digital status signals and said fourth 1-bit digital signal from the recovered third 1-bit digital signal, and (2) a digital portion of a sigma-delta codec to convert said fourth 1-bit digital signal to digital modem signals.

39. The electrical isolation barrier of claim 38 wherein the second demultiplexor includes a second frame detection circuit to detect the alignment of the digital status signals.

50. The electrical isolation barrier of claim 30 wherein the separation in the first multiplexor is accomplished using filter banks.

40. A multiplexor for use in a data access arrangement, comprising

a first input for receiving a 1-bit digital signal;

a second input for receiving a first number of digital status or control bits;

a framing circuit for combining a second number of framing bits with the first number of digital status or control bits according to a first framing pattern to form a third number of framing output bits, wherein said third number is equal to the sum of the first and second numbers; and

an interleaver which interleaves said third number of framing output bits with a proportional number of bits from the first input, forming a fourth number of multiplexor output bits;

wherein said first framing pattern uniquely indicates the correct framing alignment position of said framing output bits for all combinations of said status or control bits.

41. The multiplexor of claim 40, wherein said first framing pattern prevents the framing output bits from containing a second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

42. The multiplexor of claim 41, wherein said first framing pattern prevents the framing output bits from containing the logical inverse of said second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

43. A pair of multiplexors each located on opposite sides of an electrical isolation barrier, each of said multiplexors including

a first input for receiving a 1-bit digital signal;

a second input for receiving a first number of digital status or control bits;

a framing circuit for combining a second number of framing bits with the first number of digital status or control bits according to a first framing pattern to form a third number of framing output bits, wherein said third number is equal to the sum of the first and second numbers; and

an interleaver which interleaves said third number of framing output bits with a proportional number of bits from the first input, forming a fourth number of multiplexor output bits;

wherein the first framing pattern of each multiplexor is equal to the second framing pattern of the other.

44. A multiplexing method providing multiplexor output bits for use in a data access arrangement, comprising

receiving a first 1-bit digital signal;

receiving a first number of digital status or control bits;

providing a second number of framing bits;

providing a first framing pattern;

combining the second number of framing bits with the first number of digital status or control bits according to the first framing pattern to form a third number of framing output bits, wherein said third number is equal to the sum of the first and second numbers; and

interleaving said third number of framing output bits with a proportional number of bits from the first 1-bit digital signal to form a fourth number of multiplexor output bits;

wherein said first framing pattern uniquely indicates the correct framing alignment position of the framing output bits for all combinations of said status or control bits.

45. The method of claim 44, wherein said first framing pattern prevents the framing output bits from containing a second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

46. The method of claim 45, wherein said first framing pattern prevents the third number of framing output bits from containing the logical inverse of said second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

47. The method of claim 46, wherein said first framing pattern and said second framing pattern are interchangeable.

49. The method of transmitting a transmit signal and a receive signal in different directions concurrently through a single HF transformer, including the steps of:

operating the HF transformer in its linear range of operation; and

providing two HF hybrid circuits to separate the transmit signal for transmission in a first direction through the HF transformer and the receive signal for transmission in a second direction through the HF transformer.

51. An electrical isolation barrier for use in a data access arrangement for providing electrical isolation between a system side circuit and a line side circuit, comprising, in combination:

an HF transformer having a desired frequency range of operation, and having a first port and a second port;

a first modulator coupled to first port of said transformer through a first HF hybrid circuit, said first modulator modulating a first 1-bit digital signal to a first analog pass band signal within said desired frequency range and transmitting the modulated signal to said transformer;

a first demodulator coupled to said second port of said transformer through a second HF hybrid circuit, said demodulator demodulating said first pass band signal to recover said first 1-bit digital signal for transmission to said line side circuit.

a second modulator coupled to said second port of said transformer through said second HF hybrid circuit, said second modulator modulating a third 1-bit digital signal to a second analog pass band signal within said desired frequency range and transmitting it to said transformer;

a second demodulator coupled to said first port of said transformer through said first HF hybrid circuit, said second demodulator demodulating said second pass band signal to recover said third 1-bit digital signal for transmission to said system side circuit;

a digital portion of a sigma-delta codec included in said system side circuit for converting digital modem signals to a second 1-bit digital signal and converting a fourth 1-bit digital signal to digital modem signals;

a first multiplexor included in the system side circuit and connected to said first modulator, said first multiplexor receiving digital control signals and said second 1-bit digital signal and multiplexing them to form said first 1-bit digital signal;

a first demultiplexor included in the line side circuit and connected to the first demodulator, said first demultiplexor separating the digital control signals and second 1-bit digital signal from the recovered first 1-bit digital signal;

an analog portion of a sigma-delta codec included in the line side circuit, said analog portion converting an analog receive signal to a fourth 1-bit digital signal and converting a second 1-bit digital signal to an analog transmit signal;

a second multiplexor included in the line side circuit and connected to said second modulator, said second multiplexor receiving digital status signals and said fourth 1-bit digital signal and combining them to form said third 1-bit digital signal;

a second demultiplexor included in the system side circuit and connected to the second demodulator, said second demultiplexor recovering said digital status signals and said fourth 1-bit digital signal from the recovered third 1-bit digital signal.

52. The electrical isolation barrier of claim 51 wherein

the first multiplexor includes a first frame generation circuit to align the digital control signals;

the first demultiplexor includes a first frame detection circuit to detect the alignment of the digital control signals;

the second multiplexor includes a second frame generation circuit to align the digital status signals; and

the second demultiplexor includes a second frame detection circuit to detect the alignment of the digital status signals.