Quadrature receiver sampling architecture

• US 20030215027A1
• Filed: 06/28/2002
• Published: 11/20/2003
• Est. Priority Date: 05/17/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Jaffe, Steven, Yu, Tommy, Krafft, Stephen Edward
• Granted Patent: US 7,139,332 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H04L 27/00 Modulated-carrier systems

Abstract

Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Claims

1. A communication receiver, comprising:

an analog front-end that is operable to receive an analog I stream and an analog Q stream;

a digital processing unit that is communicatively coupled to the analog front-end;

wherein the analog front-end comprises a multiplexor and a single analog to digital converter that operate cooperatively to perform alternative digital sampling of the analog I stream and the analog Q stream thereby converting the analog I stream and the analog Q stream into a digital I stream and a digital Q stream; and

the digital processing unit is operable to perform decimation and de-rotation of a digital sample of at least one of the digital I stream and the digital Q stream, the rotation being introduced during the analog to digital conversion of at least one of the analog I stream and the analog Q stream.

2. The communication receiver of claim 1, further comprising a radio frequency interface that is operable to extract at least one of the analog I stream and an analog Q stream from a received analog signal.

3. The communication receiver of claim 1, wherein a selector of the multiplexor selector and the single analog to digital converter being clocked at a frequency that is substantially twice the digital sampling frequency of the analog I stream and the analog Q stream.

4. The communication receiver of claim 1, wherein a selector of the multiplexor selector being clocked a first frequency that is substantially twice the digital sampling frequency of the analog I stream and the analog Q stream;

and

the single analog to digital converter being clocked at a second frequency that is substantially twice the digital sampling frequency of the analog I stream and the analog Q stream.

5. The communication receiver of claim 1, wherein the analog front-end further comprises a sample and hold element that is communicatively coupled to the multiplexor.

6. The communication receiver of claim 5, wherein the analog I stream and the analog Q stream are provided to the multiplexor;

the output of the multiplexor is provided to a sample and hold element; and

the output of the sample and hold element is provided to the single analog to digital converter.

7. The communication receiver of claim 5, wherein the analog front-end further comprises further comprising at least one additional sample and hold element;

and

wherein the analog I stream is provided to the sample and hold element;

the analog Q stream is provided to the at least one additional sample and hold element;

outputs from the sample and hold element and the at least one additional sample and hold element are provided to the multiplexor; and

the output of the multiplexor is provided to the single analog to digital converter.

8. The communication receiver of claim 1, wherein the digital processing unit further comprises a digital signal processor, a delay element, and a half band interpolating filter;

the delay provided by the delay element is substantially comparable to a time comprises a duration that is substantially comparable to a time required to perform the half band interpolating filtering; and

wherein the delay element and the half band interpolating filter operate cooperatively to compensate for any delay that may have occurred during the analog to digital conversion of at least one of the analog I stream and the analog Q stream thereby performing the de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream.

9. The communication receiver of claim 1, wherein the digital processing unit further comprises a digital signal processor;

and

wherein the digital signal processor performs mathematical operations on at least one of the digital I stream and the digital Q stream to compensate for any delay that may have occurred during the analog to digital conversion of at least one of the analog I stream and the analog Q stream thereby performing the de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream.

10. The communication receiver of claim 1, wherein the analog front end further comprising:

an up-sampler, communicatively coupled to the single analog to digital converter, that is operable to increase a sample rate of at least one of the digital I stream and the digital Q stream thereby generating an over-sampled digital data stream;

an interpolation filter, communicatively coupled to the up-sampler, that is operable to remove a spectral repeat from the over-sampled digital data stream;

a variable interpolation/decimation filter, communicatively coupled to interpolation filter, that is operable to recover a transmitted symbol from the over-sampled digital data stream; and

wherein the single analog to digital converter being clocked at a frequency that comprises less than twice the highest frequency component in the received analog signal.

11. The communication receiver of claim 1, wherein the communication receiver comprises at least one of a base station receiver, a mobile receiver, a set top box, a tower receiver, a mobile unit, and an HDTV set top box receiver.

12. The communication receiver of claim 11, wherein at least one of the base station receiver and the tower receiver comprises a wireless tower.

13. The communication receiver of claim 11, wherein at least one of the set top box and the HDTV set top box receiver comprises a local satellite dish.

14. The communication receiver of claim 1, wherein the communication receiver is contained within a transceiver, the transceiver also comprises a communication transmitter.

15. The communication receiver of claim 1, wherein the analog signal is received via a wireless communication channel.

16. A satellite communication system, comprising:

a local satellite dish that is operable to receive an analog signal transmitted from a satellite via a wireless communication channel; and

a set top box, communicatively coupled to the local satellite dish via a coaxial cable, that receives the analog signal received by the local satellite dish and is operable to extract an analog I stream and an analog Q stream there from; and

wherein the set top box comprises an analog front-end and a digital processing unit, the analog front-end comprising a radio frequency interface;

the analog front-end is operable to receive the analog signal transmitted from the satellite and to extract an analog I stream and an analog Q stream there from;

the digital processing unit is communicatively coupled to the analog front-end;

the analog front-end comprises a multiplexor and a single analog to digital converter that operate cooperatively to perform alternative digital sampling of the analog I stream and the analog Q stream thereby converting the analog I stream and the analog Q stream into a digital I stream and a digital Q stream; and

the digital processing unit is operable to perform decimation and de-rotation of a digital sample of at least one of the digital I stream and the digital Q stream, the rotation being introduced during the analog to digital conversion of at least one of the analog I stream and the analog Q stream.

17. The satellite communication system of claim 16, wherein the analog front-end further comprises a radio frequency interface that is operable to extract the at least one of the analog I stream and an analog Q stream from the received analog signal.

18. The satellite communication system of claim 16, wherein the analog front-end further comprises a sample and hold element that is communicatively coupled to the multiplexor.

19. The satellite communication system of claim 16, wherein the digital processing unit further comprises a digital signal processor, a delay element, and a half band interpolating filter;

the delay provided by the delay element is substantially comparable to a time comprises a duration that is substantially comparable to a time required to perform the half band interpolating filtering; and

wherein the delay element and the half band interpolating filter operate cooperatively to compensate for any delay that may have occurred during the analog to digital conversion of at least one of the analog I stream and the analog Q stream thereby performing the de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream.

20. The satellite communication system of claim 16, wherein the analog front end further comprising:

an up-sampler, communicatively coupled to the single analog to digital converter, that is operable to increase a sample rate of at least one of the digital I stream and the digital Q stream thereby generating an over-sampled digital data stream;

an interpolation filter, communicatively coupled to the up-sampler, that is operable to remove a spectral repeat from the over-sampled digital data stream;

a variable interpolation/decimation filter, communicatively coupled to interpolation filter, that is operable to recover a transmitted symbol from the over-sampled digital data stream; and

wherein the single analog to digital converter being clocked at a frequency that comprises less than twice the highest frequency component in the received analog signal.

21. A quadrature receiver sampling method, comprising:

receiving an analog I stream and an analog Q stream;

alternatively converting the analog I stream and the analog Q stream into a digital I stream and a digital Q stream;

performing decimation of a digital sample of at least one of the digital I stream and the digital Q stream; and

performing de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream; and

wherein the rotation being introduced during the analog to digital conversion of at least one of the analog I stream and the analog Q stream; and

the alternative conversion of the analog I stream and the analog Q stream into the digital I stream and the digital Q stream being performed using a single analog to digital converter.

22. The method of claim 21, further comprising sampling and holding the analog I stream and the analog Q stream before alternatively converting the analog I stream and the analog Q stream into the digital I stream and the digital Q stream.

23. The method of claim 21, further comprising multiplexing the analog I stream and the analog Q stream before alternatively converting the analog I stream and the analog Q stream into the digital I stream and the digital Q stream.

24. The method of claim 21, wherein the frequency that is used by the single analog to digital converter to perform the alternative conversion of the analog I stream and the analog Q stream into the digital I stream and the digital Q stream substantially at least twice the highest frequency component in at least one of the received analog I stream and the analog Q stream.

25. The method of claim 21, further comprising:

receiving an analog signal;

extracting the analog I stream and the analog Q stream from the received analog signal;

digitally sampling at least one of the analog I stream and the analog Q stream a frequency that is at least twice the highest frequency component in the received analog signal thereby generating a digital signal;

up-sampling the digital signal thereby generating an over-sampled digital data stream;

removing a spectral repeat from the over-sampled digital data stream; and

recovering a transmitted symbol from the over-sampled digital data stream.

26. The method of claim 21, extracting at least one of the analog I stream and the analog Q stream from a received analog signal;

digitally sampling the analog I stream and the analog Q stream using a frequency that is at least twice the highest frequency component in the received analog signal, to generate a digital signal;

up-sampling the digital signal thereby increasing the sample rate of the digital signal by a factor of two thereby generating an over-sampled digital data stream;

removing a spectral repeat from the over-sampled digital data stream;

recovering a transmitted symbol from the over-sampled digital data stream; and

increasing a symbol rate of the recovered transmitted symbol by a factor of two.

27. The method of claim 21, wherein the method is performed within at least one of a receiver, a transceiver, base station receiver, a mobile receiver, a set top box, a tower receiver, a mobile unit, and an HDTV set top box receiver.

28. The method of claim 27, wherein at least one of the set top box and the HDTV set top box receiver comprises a local satellite dish.

29. The method of claim 21, wherein the analog signal is received via a wireless communication channel.

30. The method of claim 21, wherein the performing of the decimation and the performing of the de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream is performed within a digital signal processor.

31. A quadrature receiver sampling method, comprising:

receiving an analog signal;

extracting an analog I stream and an analog Q stream from the analog signal;

sampling and holding the analog I stream and the analog Q stream using a frequency that is at least twice the highest frequency component in the received analog signal;

multiplexing the analog I stream and the analog Q stream, the selection of the multiplexing being performed using a frequency that is substantially twice the sampling frequency;

alternatively converting the analog I stream and the analog Q stream into a digital I stream and a digital Q stream, the alternative conversion being performed using the frequency that is substantially twice the sampling frequency;

performing decimation of a digital sample of at least one of the digital I stream and the digital Q stream; and

performing de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream; and

wherein the rotation being introduced during the analog to digital conversion of at least one of the analog I stream and the analog Q stream; and

the alternative conversion of the analog I stream and the analog Q stream into the digital I stream and the digital Q stream being performed using a single analog to digital converter.

32. The method of claim 31, wherein the method is performed within at least one of a receiver, a transceiver, base station receiver, a mobile receiver, a set top box, a tower receiver, a mobile unit, and an HDTV set top box receiver.

33. The method of claim 32, wherein at least one of the set top box and the HDTV set top box receiver comprises a local satellite dish.

34. The method of claim 31, wherein the analog signal is received via a wireless communication channel.

35. The method of claim 31, wherein at least one of the performing of the decimation and the performing of the de-rotation of the digital sample of the at least one of the digital I stream and the digital Q stream is performed within a digital signal processor.