Method and apparatus for adaptive CPU power management

• US 20030217296A1
• Filed: 05/15/2002
• Published: 11/20/2003
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ma, Kenneth
• Granted Patent: US 7,010,708 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A method and apparatus are disclosed for performing adaptive run-time power management in a system employing a CPU and an operating system. A CPU cycle tracker (CCT) module monitors critical CPU signals and generates CPU performance data based on the critical CPU signals. An adaptive CPU throttler (THR) module uses the CPU performance data, along with a CPU percent idle value fed back from the operating system, to generate a CPU throttle control signal during predefined run-time segments of the CPU run time. The CPU throttle control signal links back to the CPU and adaptively adjusts CPU throttling and, therefore, power usage of the CPU during each of the run-time segments.

Claims

1. In a system employing a CPU and an operating system, a method for performing adaptive run-time power management of said CPU, said method comprising:

generating a set of boot-time profiles during a CPU boot time, said boot-time profiles corresponding to CPU performance of known code segments run during said boot time;

generating run-time parameter blocks during CPU run time, said run-time parameter blocks storing key processing performance parameters corresponding to predefined run-time segments of said CPU run time;

monitoring said CPU during said CPU run time for a CPU percent idle value and a corresponding time stamp; and

generating a CPU throttle control signal for a next run-time segment based on at least one of said set of boot-time profiles, a sliding window of said run-time parameter blocks, and a last monitored CPU percent idle value and time stamp, such that said CPU throttle control signal adjusts CPU throttling and, therefore, power consumption of said CPU during each of said run-time segments.

2. The method of claim 1 wherein generating said set of boot-time profiles comprises running an auto-profiler (APF) software module at said CPU boot time.

3. The method of claim 1 wherein said set of boot-time profiles comprises CPU performance data generated by running various CPU, memory, and I/O intensive code segments and correlating bus cycle behavior to CPU percent load.

4. The method of claim 1 wherein said known code segments correspond to at least one of 3D graphics, scientific computations, CAD functions, video decoding, and file copying.

5. The method of claim 1 wherein said key processing performance parameters comprise at least one of:

a total number of CPU accesses per unit time;

a total number of memory data read/write accesses per unit time;

a peak/average read cycle density;

a peak/average write cycle density;

a read-to-write ratio;

a percent of consecutive read accesses;

a percent of consecutive write accesses; and

a number of spikes in cycle density that pass peak density on an accumulated average basis.

6. The method of claim 1 wherein said CPU percent idle value and said time stamp are generated by an idle loop software module of said operating system.

7. The method of claim 1 wherein said CPU throttle control signal is generated, at least in part, by a predictive algorithm.

8. The method of claim 1 wherein said CPU throttle control signal comprises a CPU stop clock signal that is a digital logic high during at least a portion of each of said run-time segments.

9. The method of claim 1 wherein said CPU throttle control signal comprises a CPU stop clock signal that is a digital logic low during at least a portion of each of said run-time segments.

10. The method of claim 1 wherein a level of said CPU throttling for a particular run-time segment is defined by a duty cycle of said CPU throttle control signal for said particular run-time segment.

11. The method of claim 1 wherein said CPU stops processing when said CPU throttle control signal is in a first logic state and said CPU begins processing when said CPU throttle control signal is in a second logic state.

12. The method of claim 1 wherein said predefined run-time segments are programmable.

13. In a system employing a CPU and an operating system, apparatus for performing adaptive run-time power management of said CPU, said apparatus comprising:

a CPU cycle tracker (CCT) module that monitors critical CPU signals and generates CPU performance data based on said critical CPU signals; and

an adaptive CPU throttler (THR) module that generates a CPU throttle control signal based on said CPU performance data during predefined run-time segments of a CPU run time such that said CPU throttle control signal adjusts CPU throttling and, therefore, power consumption of said CPU during each of said run-time segments.

14. The apparatus of claim 13 wherein said CCT module comprises a CPU bus interface unit (BIU) module to enable monitoring of said critical CPU signals by said CCT module.

15. The apparatus of claim 13 wherein said CCT module comprises a cycle decoder module to track and count cycle types and addresses and correlate addresses between non-consecutive cycles as part of generating said CPU performance data.

16. The apparatus of claim 13 wherein said CPU performance data comprises:

a set of boot-time profiles generated by said CCT module during a CPU boot time, said boot-time profiles corresponding to CPU performance of known code segments run during said boot time;

run-time parameter blocks generated by said CCT module during said CPU run time, said run-time parameter blocks storing key processing performance parameters corresponding to said predefined run-time segments of said CPU run time; and

a CPU percent idle value and a corresponding time stamp.

17. The apparatus of claim 16 wherein said adaptive CPU throttler (THR) module comprises a sliding window selector (SWS) module to select a sliding window subset of said run-time parameter blocks generated by said CCT module wherein said sliding window subset covers an integer number of said predefined run-time segments of said CPU run time.

18. The apparatus of claim 17 wherein said adaptive CPU throttler (THR) module further comprises a predictor (PDT) module to adaptively generate a CPU throttling percentage value for a next run time segment based on at least one of said set of boot time profiles, said sliding window subset of said run-time parameter blocks, accumulated average parameter data, and a last generated CPU percent idle value and time stamp.

19. The apparatus of claim 18 wherein said adaptive CPU throttler (THR) module further comprises a sliding window parameter (SLD PRM) module wherein said accumulated average parameter data is generated by said PDT module in response to said sliding window subset of said run-time parameter blocks and is stored in said SLD PRM module.

20. The apparatus of claim 18 wherein said adaptive CPU throttler (THR) module further comprises a state machine generating said CPU throttle control signal based on using said CPU percent idle value and said CPU throttling percentage value such that said CPU throttle control signal is compliant with CPU protocol and timing requirements.

21. The apparatus of claim 16 wherein said CCT module employs an auto-profiler (APF) software module to generate said set of boot-time profiles.

22. The apparatus of claim 16 wherein said operating system and CPU employ an idle loop software module to generate said CPU percent idle value and said time stamp.

23. The apparatus of claim 18 wherein said PDT module employs a predictive algorithm to adaptively generate said CPU throttling percentage value.

24. The apparatus of claim 16 wherein said set of boot-time profiles comprises CPU performance data generated by running various CPU, memory, and I/O intensive code segments and by correlating bus cycle behavior to CPU percent load.

25. The apparatus of claim 16 wherein said known code segments correspond to at least one of 3D graphics, scientific computations, CAD functions, video decoding, and file copying.

26. The apparatus of claim 16 wherein said key processing performance parameters comprise at least one of:

a total number of CPU accesses per unit time;

a total number of memory data read/write accesses per unit time;

a peak/average read cycle density;

a peak/average write cycle density;

a read-to-write ratio;

a percent of consecutive read accesses;

a percent of consecutive write accesses; and

a number of spikes in cycle density that pass peak density on an accumulated average basis.

27. The apparatus of claim 13 wherein said CPU throttle control signal comprises a CPU stop clock signal that is a digital logic high during at least a portion of each of said predefined run-time segments during said CPU run time.

28. The apparatus of claim 13 wherein said CPU throttle control signal comprises a CPU stop clock signal that is a digital logic low during at least a portion of each of said predefined run-time segments during said CPU run time.

29. The apparatus of claim 13 wherein a level of said CPU throttling for a particular run-time segment is defined by a duty cycle of said CPU throttle control signal for said particular run-time segment.

30. The apparatus of claim 13 wherein said CPU stops processing when said CPU throttle control signal is in a first digital logic state and said CPU begins processing when said CPU throttle control signal is in a second digital logic state.

31. The apparatus of claim 13 wherein said predefined run-time segments are programmable.

32. In a system employing a CPU and an operating system, a method for performing adaptive run-time power management of said CPU, said method comprising:

generating at least one CPU parameter indicative of a processing aspect of said CPU;

monitoring said CPU during said CPU run time for a CPU percent idle value and a corresponding time stamp; and

generating a CPU throttle control signal for a next run-time segment based on said at least one CPU parameter and a last monitored CPU percent idle value and time stamp, such that said CPU throttle control signal adjusts CPU throttling and, therefore, power consumption of said CPU during said next run-time segment.