Design method of semiconductor device

• US 20030217344A1
• Filed: 05/20/2002
• Published: 11/20/2003
• Est. Priority Date: 03/21/2001
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ito, Yuko, Isomura, Satoru
• Granted Patent: US 6,760,895 B2
• Time in Patent Office: Days
• US Class Current: 716/6
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk. The method calculates the delay by using the total capacitance in consideration of the actual load after the layout and wiring, carries out the layout, wiring and modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the delay by using the total capacitance in consideration of the actual load and crosstalk, carries out the modification of wiring repeatedly until targeted in-cycle transfer becomes attainable, calculates the crosstalk noise by using the total capacitance and coupling capacitance in consideration of the actual load, carries out the modification of wiring repeatedly until malfunctioning subsides, and uses data after the final layout and wiring for mask data.

Claims

1. A design method of semiconductor device comprising:

a first step of calculating delay in consideration of the actual load after the layout and wiring and by using a total capacitance (Ctotal) of a subject line with the assumption of grounding of all lines except for the subject line, judging as to whether or not a targeted in-cycle transfer is attainable, and carrying out the layout and wiring repeatedly until the targeted in-cycle transfer becomes attainable;

a second step of calculating the delay in consideration of the actual load after the layout and wiring and of crosstalk and by using the total capacitance (Ctotal), judging as to whether or not the targeted in-cycle transfer is attainable, and modifying the wiring repeatedly until the targeted in-cycle transfer becomes attainable;

a third step of calculating the crosstalk noise level in consideration of the actual load after the layout and wiring carried out by the second step and by using the total capacitance (Ctotal) and a coupling capacitance (Cp) between the subject line and an adjacent line, judging as to whether or not malfunctioning occurs, and modifying the wiring repeatedly until malfunctioning subsides; and

a fourth step of using data after the layout and wiring carried out by the third step for mask data.

2. A semiconductor device design method according to claim 1, wherein the first step further evaluating a capacitance increment (Δ

Cp) of the total capacitance (Ctotal) of the subject line for the cases with and without an adjacent line, modifying the layout and wiring route for a net which has a negative slack even in the case of no capacitance increment (Δ

Cp=0) of the case without an adjacent line, and removing an adjacent line for a net which has no negative slack in the case of no capacitance increment (Δ

Cp=0) of the case without an adjacent line, but has a negative slack in the case with a capacitance increment (Δ

Cp>

0) of the case with an adjacent line.

3. A semiconductor device design method according to claim 2, wherein in evaluating the total capacitance (Ctotal), total capacitance values of unit length, with the assumption of the whole capacitance of the subject line to be the line-to-ground capacitance, are registered in advance in a table in relation with parameters in terms of the modulus of parallelism and modulus of crossing, the actual modulus of parallelism and modulus of crossing are calculated based on layout data after the layout and wiring, the total capacitance value of unit length corresponding to the calculated modulus of parallelism and modulus of crossing is evaluated based on the interpolation or extrapolation process for the contents of the table, and the length of the subject line is multiplied to the evaluated total capacitance of unit length, thereby evaluating the total capacitance (Ctotal).

4. A semiconductor device design method according to claim 3, wherein the total capacitance values of unit length registered in the table in relation with the parameters of modulus of parallelism and modulus of crossing are evaluated for an arbitrary number of models having different densities of adjacent lines and different densities of cross lines.

5. A semiconductor device design method according to claim 2, wherein in evaluating the coupling capacitance (Cp), coupling capacitance values of unit length between the subject line and the adjacent line are registered in advance in a table in relation with a parameter in terms of the modulus of crossing of the subject line, the actual modulus of crossing is calculated based on layout data after the layout and wiring, the coupling capacitance of unit length corresponding to the calculated modulus of crossing is evaluated based on the interpolation or extrapolation process for the contents of the table, and the length of the subject line is multiplied to the evaluated coupling capacitance of unit length, thereby evaluating the coupling capacitance (Cp).

6. A semiconductor device design method according to claim 5, wherein the coupling capacitance values of unit length registered in the table in relation with the parameter of modulus of crossing are evaluated for an arbitrary number of models having different densities of adjacent lines and different densities of cross lines.

7. A semiconductor device design method according to claim 2, wherein in evaluating the capacitance increment (Δ

Cp), capacitance increment values of unit length due to the presence of adjacent lines out of the total capacitance (Ctotal) are registered in advance in a table in relation with a parameter in terms of the modulus of crossing, the actual modulus of crossing is calculated based on layout data after the layout and wiring, the capacitance increment of unit length corresponding to the calculated modulus of crossing is evaluated based on the interpolation or extrapolation process for the contents of the table, and the length of the subject line is multiplied to the evaluated capacitance increment of unit length, thereby evaluating the capacitance increment (Δ

Cp).

8. A semiconductor device design method according to claim 7, wherein the capacitance increment values of unit length registered in the table in relation with the parameter of modulus of crossing are evaluated for an arbitrary number of models having different densities of cross lines.

9. A semiconductor device design method according to claim 2, wherein the line-to-ground capacitance included in the total capacitance (Ctotal) is defined by being separated into a base capacitance inherent to the existence of the subject line, a cross capacitance increment caused by a cross line, and a parallel capacitance increment caused by an adjacent line.

10. A semiconductor device design method according to any of claims 3, 4, 5, 6, 7 and 8, wherein the subject line and adjacent line have aspect ratios of line cross section of 1 or larger.