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Method and Apparatus for Quantifying the Quality of Placement Configurations in a Partitioned Region of an Integrated Circuit Layout

  • US 20030217346A1
  • Filed: 12/19/2000
  • Published: 11/20/2003
  • Est. Priority Date: 12/06/2000
  • Status: Active Grant
First Claim
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1. For an electronic design automation application, a partitioning method of placing circuit modules in a region of an integrated circuit (“

  • IC”

    ) layout, wherein said IC layout includes nets and a plurality of circuit elements, each net representing interconnections between a set of circuit elements in the IC layout, the method comprising;

    a) defining a plurality of partitioning lines that divide the IC region into several sub-regions;

    b) identifying the set of sub-regions containing the circuit elements of a net, said set of sub-regions representing the net'"'"'s configuration with respect to the defined partitioning lines;

    wherein a connection graph models the net'"'"'s configuration with respect to the defined partitioning lines;

    said connection graph having an edge that is completely or partially diagonal; and

    c) identifying an attribute of the connection graph.

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