Nonvolatile memory device

• US 20030218205A1
• Filed: 03/19/2003
• Published: 11/27/2003
• Est. Priority Date: 03/22/2002
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Takamura, Takashi
• Granted Patent: US 6,809,374 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation

Abstract

To match where electrons are injected when writing and where holes are injected when erasing in a MONOS-type nonvolatile memory device, two control gates are formed between a word gate on respective intervening ONO gate insulation layers which, in turn, are formed on a substrate. The third layers (silicon oxide layer) are absent over respective portions of the second layers along the lengths of the second gate insulation layers to form shoulders. The electron injection position when writing and the hole injection position when erasing can thus be confined to the neighborhood of the shoulder(s) where the third layer is removed.

Claims

1. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a word gate formed above the channel region;

a first gate insulation layer between the word gate and the channel region;

a first control gate formed to one side of the word gate;

a first side insulation layer between the first control gate and the word gate;

a second control gate formed to another side of the word gate;

a second side insulation layer between the second control gate and the word gate;

a second gate insulation layer having a first charge trapping region formed between the substrate and the first control gate; and

a third gate insulation layer having a second charge trapping region formed between the substrate and second control gate;

wherein the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and the first control gate is lower within a first range in a gate length direction adjacent the first side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.

2. A nonvolatile memory device as described in claim 1, wherein the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and the second control gate is lower within a third range in the gate length direction adjacent the second side insulation layer than it is within a fourth range in the gate length direction closer to the second impurity region.

3. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a word gate formed above the channel region;

a first gate insulation layer between the word gate and the channel region;

a first control gate formed to one side of the word gate;

a first side insulation layer between the first control gate and the word gate;

a second control gate formed to another side of the word gate;

a second side insulation layer between the second control gate and the word gate;

a second gate insulation layer having a first charge trapping region formed between the substrate and the first control gate; and

a third gate insulation layer having a second charge trapping region formed between the substrate and second control gate;

wherein a film of the second gate insulation layer is thicker within a first range in a gate length direction adjacent the first side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.

4. A nonvolatile memory device as described in claim 3, wherein a film of the third gate insulation layer is thicker within a third range in the gate length direction adjacent the second side insulation layer than it is within a fourth range in the gate length direction closer to the second impurity region.

5. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a word gate formed above the channel region;

a first gate insulation layer between the word gate and the channel region;

a first control gate formed to one side of the word gate;

a first side insulation layer between the first control gate and the word gate;

a second control gate formed to another side of the word gate;

a second side insulation layer between the second control gate and the word gate;

a second gate insulation layer having a first charge trapping region formed between the substrate and the first control gate; and

a third gate insulation layer having a second charge trapping region formed between the substrate and second control gate;

wherein the second gate insulation layer comprises a multiple layer film including a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer of the second gate insulation layer being in contact with the first control gate within a first range in a gate length direction in proximity to the first impurity region.

6. A nonvolatile memory device as described in claim 5, wherein the third gate insulation layer comprises a multiple layer film including a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer of the third gate insulation layer being in contact with the second control gate within a second range in a gate length direction in proximity to the second impurity region.

7. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a word gate formed above the channel region;

a first gate insulation layer between the word gate and the channel region;

a control gate formed to one side of the word gate;

a side insulation layer between the control gate and the word gate; and

a second gate insulation layer having a charge trapping region formed between the substrate and the control gate;

wherein the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and the control gate is lower within a first range in a gate length direction adjacent the side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.

8. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a word gate formed above the channel region;

a first gate insulation layer between the word gate and the channel region;

a control gate formed to one side of the word gate;

a side insulation layer between the control gate and the word gate; and

a second gate insulation layer having a charge trapping region formed between the substrate and the control gate;

wherein a film of the second gate insulation layer is thicker within a first range in a gate length direction adjacent the side insulation layer than it is within a second range in the gate length direction closer to the first impurity region.

9. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a word gate formed above the channel region;

a first gate insulation layer between the word gate and the channel region;

a control gate formed to one side of the word gate;

a side insulation layer between the control gate and the word gate; and

a second gate insulation layer having a charge trapping region formed between the substrate and the control gate;

wherein the second gate insulation layer comprises a multiple layer film including a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer being in contact with the control gate within a range in a gate length direction in proximity to the second impurity region.

10. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a control gate formed above the channel region; and

a gate insulation layer between the control gate and the channel region;

wherein the magnitude of an electric field applied in a direction substantially orthogonal relative to the substrate surface between the substrate and control gate is lower within a middle region in the gate length direction of the control gate than it is in regions closer to the first and second impurity regions.

11. A nonvolatile memory device, comprising:

a first impurity region and a second impurity region each formed in a substrate;

a channel region between the first and second impurity regions;

a control gate formed above the channel region; and

a gate insulation layer between the control gate and the channel region;

wherein the gate insulation layer comprises a multiple layer film including a silicon nitride layer disposed between top and bottom silicon oxide layers, the silicon nitride layer being in contact with the control gate in proximity to the first and second impurity regions.