Transistor structures and methods for making the same
First Claim
1. A field effect transistor, comprising:
- a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO2;
a gate insulator layer comprising a substantially transparent material and being located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface;
a source that can inject electrons into the channel layer for accumulation at the channel layer/gate insulator layer interface; and
a drain that can extract electrons from the channel layer;
wherein the field effect transistor is configured for enhancement-mode operation.
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Abstract
Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO2. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO or SnO2, the substantially insulating ZnO or SnO2 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.
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Citations
64 Claims
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1. A field effect transistor, comprising:
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a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO or SnO2;
a gate insulator layer comprising a substantially transparent material and being located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface;
a source that can inject electrons into the channel layer for accumulation at the channel layer/gate insulator layer interface; and
a drain that can extract electrons from the channel layer;
wherein the field effect transistor is configured for enhancement-mode operation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 52, 53, 56, 58, 60)
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18. A field effect transistor, comprising:
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a channel layer comprising a substantially transparent material selected from substantially insulating ZnO or substantially insulating SnO2, the substantially insulating ZnO or substantially insulating SnO2 being produced by annealing;
a gate insulator layer located adjacent to the channel layer;
a source;
a drain; and
a gate electrode;
wherein the field effect transistor is configured for enhancement-mode operation. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 54, 55, 57, 59, 61)
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35. A thin film transistor comprising:
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a discrete channel layer comprising an inorganic, substantially insulating material; and
a gate insulator layer located adjacent to the channel layer, wherein the combined channel layer and gate insulator layer construct exhibits an optical transmission through the construct of at least about 90% in the visible portion of the electromagnetic spectrum, and is configured for enhancement-mode operation. - View Dependent Claims (36, 37)
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38. A method for operating a field effect transistor, comprising:
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providing a field effect transistor that includes (i) a channel layer comprising a substantially insulating, substantially transparent material selected from ZnO or SnO2;
(ii) a gate insulator layer located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface (iii) a source;
(iv) a drain; and
(v) a gate electrode; and
applying a positive voltage to the gate electrode to effect a flow of electrons at the channel layer/gate insulator layer interface, wherein in the absence of an applied positive voltage substantially no current flow occurs. - View Dependent Claims (39, 40, 41)
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42. A method for making an enhancement mode, field effect transistor comprising:
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depositing ZnO or SnO2 onto at least a portion of a surface of a gate insulating layer; and
annealing the ZnO or SnO2 for about 1 to about 5 minutes at a temperature of about 300 to about 1000°
C. in an oxidative or inert atmosphere. - View Dependent Claims (43, 44, 45, 46, 47, 48, 49, 50)
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51. A method for making an enhancement mode, field effect transistor comprising:
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depositing ZnO or SnO2 onto at least a portion of a surface of a gate insulating layer; and
treating the ZnO or SnO2 such that the treated ZnO or SnO2 has a higher resistivity and a lower oxygen vacancy concentration relative to the untreated ZnO or SnO2.
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62. A microelectronic construct, comprising:
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a continuous channel layer film comprising a substantially insulating material selected from ZnO or SnO2; and
a plurality of patterned gate insulator layers, sources, and drains arranged so that each gate insulator layer, source and drain forms, along with the continuous channel layer film, a discrete electrical device, wherein the gate insulator layer is located adjacent to the continuous channel layer film so as to define a channel layer/gate insulator layer interface. - View Dependent Claims (63, 64)
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Specification