Transistor structures and methods for making the same

• US 20030218222A1
• Filed: 01/24/2003
• Published: 11/27/2003
• Est. Priority Date: 05/21/2002
• Status: Active Grant

• Current Assignee: Oregon State University (Oregon University System)
• Original Assignee: Oregon State University (Oregon University System)
• Inventors: Wager, John F. III, Hoffman, Randy L.
• Granted Patent: US 7,339,187 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, SnO₂, or In₂O₃. A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, SnO₂ or In₂O₃, the substantially insulating ZnO, SnO₂, or In₂O₃ being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

Claims

1. A field effect transistor, comprising:

a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, SnO₂, or In₂O₃;

a gate insulator layer comprising a substantially transparent material and being located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface;

a source that can inject electrons into the channel layer for accumulation at the channel layer/gate insulator layer interface; and

a drain that can extract electrons from the channel layer;

wherein the field effect transistor is configured for enhancement-mode operation.

2. The transistor according to claim 1, wherein the channel layer/gate insulator layer interface defines an electron conducting channel between the source and the drain.

3. The transistor according to claim 1, wherein the field effect transistor comprises a thin film transistor.

4. The transistor according to claim 1, wherein the channel layer material is a different material from the gate insulator layer material.

5. The transistor according to claim 1, further comprising a gate electrode and a substrate, and wherein the source, drain, gate electrode, and substrate are each made from a substantially transparent material.

6. The transistor according to claim 1, further comprising a gate electrode and a substrate, and wherein at least one of the source, drain, gate electrode, or substrate is made from an opaque material.

7. The transistor according to claim 1, wherein the gate insulator layer comprises Al₂O₃/TiO₂.

8. The transistor according to claim 5, wherein the gate insulator layer comprises Al₂O₃/TiO₂ or Al₂O₃;

the source, drain, and gate electrode each comprise indium-tin oxide; and

the substrate comprises glass.

9. The transistor according to claim 1, wherein the channel layer/gate insulator layer interface defines a discrete material boundary.

10. The transistor according to claim 1, wherein the field effect transistor exhibits an optical transmission through the field effect transistor of at least about 50% in the visible portion of the electromagnetic spectrum.

11. The transistor according to claim 10, wherein the optical transmission is at least about 90% in the visible portion of the electromagnetic spectrum.

12. The transistor according to claim 1, wherein the channel layer is not ion implanted.

13. The transistor according to claim 1, wherein the channel layer material exhibits a bandgap of less than about 5 eV.

14. The transistor according to claim 1, wherein the ZnO, SnO₂, or In₂O₃ has a reduced oxygen vacancy concentration.

44. An optoelectronic display device comprising at least one display element coupled to a switch comprising an enhancement-mode, field effect transistor according to claim 1.

45. The optoelectronic display device of claim 44, wherein the device comprises an active-matrix liquid-crystal display.

48. A substantially transparent, dynamic random-access memory cell, comprising a substantially transparent capacitor coupled to an enhancement-mode, field effect transistor according to claim 1.

50. A substantially transparent logic inverter, comprising a load device coupled to an enhancement-mode, field effect transistor according to claim 1.

52. An amplifier comprising an enhancement-mode, field effect transistor according to claim 1.

61. The transistor according to claim 1, wherein the ZnO, SnO₂, or In₂O₃ has a reduced degree of oxygen deficiency.

15. A field effect transistor, comprising:

a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, substantially insulating SnO₂, or substantially insulating In₂O₃, the substantially insulating ZnO, substantially insulating SnO₂, or substantially insulating In₂O₃ being produced by annealing;

a gate insulator layer located adjacent to the channel layer;

a source;

a drain; and

a gate electrode;

wherein the field effect transistor is configured for enhancement-mode operation.

16. The transistor according to claim 15, wherein the gate insulator layer comprises a substantially transparent material.

17. The transistor according to claim 16, wherein the gate insulator layer comprises Al₂O₃/TiO₂.

18. The transistor according to claim 15, further comprising a substrate, wherein the source, drain, gate electrode, and substrate are each made from a substantially transparent material.

19. The transistor according to claim 15, further comprising a substrate, and wherein at least one of the source, drain, gate electrode, or substrate is made from an opaque material.

20. The transistor according to claim 15, wherein the channel layer comprises insulating ZnO fabricated by annealing a ZnO film for about 1 minute to about 2 hours at a temperature of about 300 to about 1000°

C. in a substantially oxidative or inert atmosphere.

21. The transistor according to claim 20, wherein the gate insulator layer comprises Al₂O₃/TiO₂ or Al₂O₃;

the source, drain, and gate electrode each comprise indium-tin oxide; and

the substrate comprises glass.

22. The transistor according to claim 15, wherein the channel layer is interposed between the gate insulator layer and the source and drain.

23. The transistor according to claim 15, wherein the channel layer and the gate electrode are disposed, respectively, on opposing surfaces of the gate insulator layer.

24. The transistor according to claim 15, wherein the channel layer comprises undoped ZnO.

25. The transistor according to claim 15, wherein the channel layer material exhibits a bandgap of less than about 5 eV.

26. The transistor according to claim 15, wherein the channel layer is not interposed between the gate insulator layer and the source and drain.

27. The transistor according to claim 15, further comprising a substrate, and wherein the gate electrode is disposed adjacent to the substrate.

28. The transistor according to claim 15, wherein the annealed ZnO, SnO₂, or In₂O₃ has a lower oxygen vacancy concentration relative to ZnO, SnO₂ or In₂O₃ that has not been annealed.

46. An optoelectronic display device comprising at least one display element coupled to a switch comprising an enhancement-mode, field effect transistor according to claim 15.

47. The optoelectronic display device of claim 46, wherein the device comprises an active-matrix liquid-crystal display.

49. A substantially transparent, dynamic random-access memory cell, comprising a substantially transparent capacitor coupled to an enhancement-mode, field effect transistor according to claim 15.

51. A substantially transparent logic inverter, comprising a load device coupled to an enhancement-mode, field effect transistor according to claim 15.

53. An amplifier comprising an enhancement-mode, field effect transistor according to claim 15.

62. The transistor according to claim 15, wherein the annealed ZnO, SnO₂, or In₂O₃ has a lower degree of oxygen deficiency relative to ZnO, SnO₂, or In₂O₃ that has not been annealed.

29. A thin film transistor comprising:

a discrete channel layer comprising an inorganic, substantially insulating material selected from ZnO, SnO₂ or In₂O₃; and

a gate insulator layer located adjacent to the channel layer,

wherein the combined channel layer and gate insulator layer construct exhibits an optical transmission through the construct of at least about 90% in the visible portion of the electromagnetic spectrum, and is configured for enhancement-mode operation.

30. The transistor according to claim 29, wherein the combined channel layer and gate insulator layer construct exhibits an optical transmission through the construct of at least about 95% in the visible portion of the electromagnetic spectrum.

31. The transistor according to claim 30, wherein the channel layer comprises insulating ZnO.

32. A method for operating a field effect transistor, comprising:

providing a field effect transistor that includes (i) a channel layer comprising a substantially insulating, substantially transparent material selected from ZnO, SnO₂, or In₂O₃;

(ii) a gate insulator layer located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface (iii) a source;

(iv) a drain; and

(v) a gate electrode; and

applying a positive voltage to the gate electrode to effect a flow of electrons at the channel layer/gate insulator layer interface, wherein in the absence of an applied positive voltage substantially no current flow occurs.

33. The method according to claim 32, wherein the gate insulating layer comprises a substantially transparent material.

34. The method according to claim 32, wherein the electrons flowing at the channel layer/gate insulator layer interface have an effective mobility of about 0.05 cm²V⁻

1s<sup>−

1</sup> to about 20 cm²V<sup>−

1</sup>s<sup>−

1</sup>.

35. The method according to claim 32, wherein a voltage of about 5 to about 40 V is applied to the gate electrode and the drain.

36. A method for making an enhancement mode, field effect transistor comprising:

depositing ZnO, SnO₂, or In₂O₃ onto at least a portion of a surface of a gate insulating layer; and

annealing the ZnO, SnO₂, or In₂O₃ for about 1 minute to about 2 hours at a temperature of about 300 to about 1000°

C. in an oxidative or inert atmosphere.

37. The method according to claim 36, wherein ZnO is deposited.

38. The method according to claim 36, wherein the gate insulator layer comprises a substantially transparent material.

39. The method according to claim 36, wherein the annealing temperature is about 700 to about 800°

C.

40. The method according to claim 36, further comprising depositing on the ZnO, SnO₂ or In₂O₃ layer at least one material for forming a source and a drain.

41. The method according to claim 36, further comprising depositing on the gate insulating layer at least one material for forming a source and a drain prior to depositing the ZnO, SnO₂, or In₂O₃.

42. The method according to claim 41, wherein the material for forming a source and a drain is ion beam sputtered deposited onto the gate insulating layer, and the annealing of the ZnO diffusion dopes the ZnO with the source and drain material.

56. The method according to claim 37, further comprising introducing an acceptor dopant into the ZnO.

57. The method according to claim 36, wherein the depositing of ZnO, SnO₂, or In₂O₃ comprises sputter depositing the ZnO, SnO₂, or In₂O₃ in an atmosphere that includes at least one sputter gas and at least one gas that can modify a film formed by the ZnO, SnO₂, or In₂O₃.

58. The method according to claim 57, wherein the film-modifying gas comprises at least one gas selected from an oxidative gas and a dopant gas.

59. The method according to claim 58, wherein the oxidative gas comprises oxygen and the dopant gas comprises nitrogen.

60. The method according to claim 36, wherein the ZnO, SnO₂, or In₂O₃ is annealed for about 1 minute to about 5 minutes.

43. A method for making an enhancement mode, field effect transistor comprising:

depositing ZnO, SnO₂ or In₂O₃ onto at least a portion of a surface of a gate insulating layer; and

treating the ZnO, SnO₂ or In₂O₃ such that the treated ZnO, SnO₂, or In₂O₃ has a higher resistivity and a lower oxygen vacancy concentration relative to the untreated ZnO, SnO₂, or In₂O₃.

54. A microelectronic construct, comprising:

a continuous channel layer film comprising a substantially insulating material selected from ZnO, SnO₂, or In₂O₃; and

a plurality of patterned gate insulator layers, sources, and drains arranged so that each gate insulator layer, source and drain forms, along with the continuous channel layer film, a discrete electrical device, wherein the gate insulator layer is located adjacent to the continuous channel layer film so as to define a channel layer/gate insulator layer interface.

55. The microelectronic construct according to claim 54, wherein the continuous channel layer film is not patterned.