Surface-mounting type of electronic circuit unit suitable for miniaturization and a method for fabricating the unit

• US 20030218233A1
• Filed: 05/19/2003
• Published: 11/27/2003
• Est. Priority Date: 05/23/2002
• Status: Active Grant

• Current Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Inventors: Yokoyama, Seiichi, Ueda, Kazuhiko
• Granted Patent: US 6,894,373 B2
• Time in Patent Office: Days
• US Class Current: 257/516
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 27/0641 without components of the field effect type
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 2201/0317 Thin film conductor layer; Thin film passive component
• CPC Class Codes: H05K 3/244 : Finish plating of conductors, especially of copper conductors, e.g. for pads or lands selective plating methods H05K3/243; finish plating of conductors made by printing techniques H05K3/246; solder as finish H05K3/3457, e.g. by plating H05K3/3473
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence

Abstract

Thin film circuit elements including capacitors, resistors, and inductance elements are formed on a large substrate, and semiconductor chips are wire bonded to the substrate. The elements and chips are sealed by potting a sealing resin. The large substrate is divided into multiple stripe substrates by dicing and a thin-film conductive layer is sputtered on cut surfaces of the stripe substrates, thereby electrically connecting edges of lower conductive patterns to edges of upper conductive patterns exposed from side surfaces of the sealing resin through the thin-film conductive layer. A Ni foundation layer and Au layer are successively plated on a surface of the thin-film conductive layer to form edge electrodes on side surfaces of the stripe substrates and the stripe substrates are divided finely into individual alumina substrates.

Claims

1. An electronic circuit unit comprising:

an alumina substrate;

thin film circuit elements including at least one capacitor, at least one resistor, and at least one inductance element formed on one surface of the alumina substrate;

an upper conductive pattern and lower conductive pattern formed on the one surface and an opposing surface of the alumina substrate, respectively, the upper and lower conductive patterns being thin films;

at least one semiconductor chip wire bonded to the upper conductive pattern;

a thermosetting resin that seals the circuit elements, upper conductive pattern, and semiconductor chip on the alumina substrate; and

an edge electrode sputtered on a side surface of the alumina substrate,

wherein an edge of the upper conductive pattern is exposed from a side surface of the thermosetting resin, and the edge electrode provides a connection between respective edges of the upper conductive pattern and the lower conductive pattern.

2. The electronic circuit unit according to claim 1, wherein a lower nickel plating layer and an upper gold plating layer are provided on the edge electrode, the nickel layer thick enough to provide adhesion of the gold layer to the edge electrode and the gold layer thick enough to reduce contact resistance of the edge electrode.

3. The electronic circuit unit according to claim 1, wherein ground electrodes are disposed near corners on a first side of the one surface and on a second side opposing the first side with non-ground electrodes disposed between the ground electrodes, and on the second side aground electrode is disposed adjacent to one of the other two ground electrodes.

4. The electronic circuit unit according to claim 3, wherein a pair of projections narrows a gap portion between at least one of the capacitors and at least one of the non-ground electrodes.

5. The electronic circuit unit according to claim 1, wherein the thin film circuit elements include at least first and second capacitors, the first capacitor has a concave shape with two rectangles projecting from one side of another rectangle, and the second capacitor has a tri-rectangular shape with three rectangles arranged continuously in a dislocated relation along a long side of the tri-rectangular shape.

6. The electronic circuit unit according to claim 1, wherein the thin film circuit elements include at least a pair of resistors and another resistor, the pair of resistors forming a voltage divider and disposed parallel and adjacent to each other, the other resistor separated by relatively large distance compared with a distance separating the pair of resistors, ratios of resistances of the pair of resistors from desired values being equal.

7. The electronic circuit unit according to claim 1, wherein the thin film circuit elements include a conductive path connected with an end of one of the inductance elements, the conductive path to increase an inductance of the one of the inductance elements and having a width and characteristic, impedance equal to that of the one of the inductance elements.

8. The electronic circuit unit according to claim 1, wherein the semiconductor chip is fixed on a connection land using conductive adhesive, the connection land having an area smaller than that of a lower surface of the semiconductor chip, the area of the conduction land small enough such that extrusion of the conductive adhesive from dimensions corresponding to semiconductor chip and shorting to the surrounding upper conductive pattern is prevented.

9. The electronic circuit unit according to claim 8, wherein an opening is provided within the connection land in which the conductive adhesive pools.

10. The electronic circuit unit according to claim 1, wherein the substrate is defined by dividing grooves of a larger substrate, the grooves extending lengthwise and crosswise and forming the side surfaces of the substrate.

11. A method for fabricating the electronic circuit unit, comprising:

forming thin film circuit elements including the capacitor, resistor, and inductance element, and upper conductive pattern connected to the circuit elements on one surface of a substrate containing an alumina material;

forming a thin film lower conductive pattern on an opposing surface of the substrate;

wire bonding the semiconductor chip to the upper conductive pattern;

potting thermosetting resin on the one surface of the substrate to seal the circuit elements, upper conductive pattern, and semiconductor chip;

dividing the substrate after potting into multiple stripe substrates;

sputtering an edge electrode on a side surface of at least one of the stripe substrates along a longitudinal direction of the at least one of the stripe substrates to thereby provide a connection between respective edges of the lower conductive pattern and the upper conductive pattern exposed from a side surface of the thermosetting resin; and

dividing the stripe substrates into individual alumina substrates finely after sputtering the edge electrode.

12. The method according to claim 11, further comprising dividing the substrate into the multiple stripe substrates by dicing in a cutting direction from a side on which the lower conductive pattern is formed to the thermosetting resin.

13. The method according to claim 11, further comprising simultaneously sputtering edge electrodes on side surfaces of a plurality of the stripe substrates along longitudinal directions of the plurality of the stripe substrates.

14. The method according to claim 11, further comprising plating a lower nickel layer and an upper gold layer on the edge electrode, the nickel layer thick enough to provide adhesion of the gold layer to the edge electrode and the gold layer thick enough to reduce contact resistance of the edge electrode.

15. The method according to claim 11, further comprising forming ground electrodes near corners on a first side of the one surface and on a second side opposing the first side, forming non-ground electrodes between the ground electrodes, and forming an additional ground electrode adjacent to one of the two ground electrodes on the second side.

16. The method according to claim 15, further comprising enabling a low voltage discharge by narrowing a gap portion between at least one of the capacitors and at least one of the non-ground electrodes.

17. The method according to claim 11, further comprising increasing capacitance of capacitors formed as thin film circuit elements and decreasing space used by the capacitors by forming the capacitors with one of a concave shape with two rectangles projecting from one side of another rectangle and a tri-rectangular shape having three rectangles arranged continuously in a dislocated relation along a long side of the tri-rectangular shape.

18. The method according to claim 11, further comprising increasing capacitance of capacitors formed as thin film circuit elements to increase a parasitic oscillation frequency to at least an operating point frequency of the transistor, thereby eliminating parasitic oscillation of the transistor.

19. The method according to claim 11, further comprising forming a voltage divider using at least a pair of resistors disposed parallel and adjacent to each other whose ratios of resistances from desired values are equal thereby eliminating trimming of the pair of resistors, and forming another resistor separated by relatively large distance compared with a distance separating the pair of resistors.

20. The method according to claim 11, further comprising increasing an inductance of one of the inductance elements by trimming a conductive path connected with an end of the one of the inductance elements, and forming the conductive path to have a width and characteristic impedance equal to that of the one of the inductance elements.

21. The method according to claim 11., further comprising fixing the semiconductor chip on a connection land having an area smaller than that of a lower surface of the semiconductor chip using conductive adhesive, and preventing extrusion of the conductive adhesive from dimensions corresponding to semiconductor chip and thus shorting to the surrounding upper conductive pattern by decreasing a ratio of the area of the conduction land to that of the lower surface of the semiconductor chip.

22. The method according to claim 21, further comprising forming an opening in the connection land and permitting the conductive adhesive to pool in the opening.

23. The method according to claim 11, further comprising forming dividing grooves that extend lengthwise and crosswise in the substrate to define the individual substrates and dividing the substrate and the stripe substrates into the individual substrates along the grooves.