Process for formation of a wiring network using a porous interlevel dielectric and related structures

• US 20030218253A1
• Filed: 12/13/2001
• Published: 11/27/2003
• Est. Priority Date: 12/13/2001
• Status: Abandoned Application

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lopatin, Sergey, Wang, Fei, Erb, Darrell M., Avanzino, Steven C.
• Application Number:
  US10/017,886
• Publication Number:
  US 20030218253A1
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02282 liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A precursor of a low-k porous dielectric is applied to an integrated circuit substrate. The precursor comprises a host thermosetting material and a porogen. Crosslinking of at least some of the first host thermosetting material is produced to form a low-k dielectric matrix without decomposing all of the porogen. This leaves a solid nonporous layer of the low-k dielectric matrix. Wiring elements are then inlaid in the low-k dielectric matrix. After the wiring elements are formed, remaining porogen is decomposed to leave pores in the low-k dielectric matrix. The resulting wiring elements are smooth walled.

Claims

1. A method for forming a wiring network of an integrated circuit, comprising:

providing an integrated circuit substrate comprising a first conductive element;

applying a precursor to the substrate, the precursor comprising a host thermosetting material and a porogen;

producing crosslinking of at least some of the host thermosetting material to form a low-k dielectric matrix without decomposing all of the porogen;

inlaying a second conductive element in the low-k dielectric matrix in contact with the first conductive element; and

decomposing remaining porogen to leave pores in the low-k dielectric matrix.

2. The method claimed in claim 1, wherein the substrate further comprises a passivation layer overlying at least the first conductive element.

3. The method claimed in claim 1, wherein the first conductive element comprises a via and the second conductive element comprises an interconnect.

4. The method claimed in claim 1, wherein the first conductive element comprises an interconnect and the second conductive element comprises a via.

5. The method claimed in claim 1, wherein said inlaying is preceded by forming a stop layer on the low-k dielectric matrix, the stop layer being permeable to decomposition products of the porogen.

6. The method claimed in claim 1, wherein said inlaying is preceded by forming a stop layer on the low-k dielectric matrix, and

wherein said decomposing is preceded by removing the stop layer.

7. The method claimed in claim 1, wherein inlaying the second conductive element is followed by selectively depositing a metal cap on the second conductive element.

8. The method claimed in claim 1, wherein inlaying the second conductive element is followed by forming a cap layer over the second conductive element and the low-k dielectric matrix.

9. The method claimed in claim 1, wherein said inlaying is preceded by forming a stop layer on the low-k dielectric matrix, and

wherein said inlaying is followed by removing the stop layer and forming a cap layer over the second conductive element and the low-k dielectric material.

10. The method claimed in claim 1, wherein producing crosslinking comprises performing thermal processing at a temperature of less than approximately 390 degrees C.

11. The method claimed in claim 1, wherein said decomposing comprises performing thermal processing at a temperature in excess of approximately 390 degrees C.

12. A wiring network of an integrated circuit, comprising:

an integrated circuit substrate comprising a first conductive element;

a second conductive element contacting the first conductive element, the second conductive element having smooth walls;

a layer of porous interlevel dielectric formed over the substrate and surrounding the second conductive element; and

a stop layer formed over the porous interlevel dielectric, the stop layer being permeable to a decomposition product of a porogen of a precursor of the porous interlevel dielectric.

13. The wiring network claimed in claim 12, wherein the second conductive element comprises:

a bulk copper material; and

a continuous layer of barrier material surrounding the bulk copper material.

14. A method for forming a wiring network of an integrated circuit, comprising:

providing an integrated circuit substrate comprising a first conductive element;

applying a first precursor to the substrate, the first precursor comprising a first host thermosetting material and a first porogen;

producing crosslinking of at least some of the first host thermosetting material to form a first low-k dielectric matrix without decomposing all of the first porogen;

forming a first stop layer over the first low-k dielectric matrix;

applying a second precursor to the first stop layer, the second precursor comprising a second host thermosetting material and a second porogen;

producing crosslinking of at least some of the second host thermosetting material to form a second low-k dielectric matrix without decomposing all of the second porogen;

forming a second stop layer over the second low-k dielectric matrix;

forming a trench defining a dual damascene structure in the first and second low-k dielectric matrixes and the first and second stop layers to expose the first conductive element;

inlaying a second conductive element in the trench in contact with the first conductive element; and

decomposing remaining first and second porogen to leave pores in the first and second low-k dielectric matrixes.

15. The method claimed in claim 14, wherein the substrate further comprises a passivation layer overlying at least the first conductive element.

16. The method claimed in claim 14, wherein the first conductive element comprises an interconnect and the second conductive element is a dual damascene structure comprising a via and an interconnect.

17. The method claimed in claim 14, wherein the second conductive element comprises a barrier material surrounding a bulk copper conductor.

18. The method claimed in claim 14, wherein the second stop layer is permeable to decomposition products of the second porogen.

19. The method claimed in claim 14, wherein the first stop layer is permeable to decomposition products of the first porogen, and

wherein the second stop layer is permeable to decomposition products of the first porogen and decomposition products of the second porogen contained in the second precursor.

20. The method claimed in claim 14, wherein producing crosslinking of the second host material is preceded by removing the second stop layer.

21. The method claimed in claim 14, wherein inlaying the second conductive element is followed by selectively depositing a metal cap on the second conductive element.

22. The method claimed in claim 14, wherein inlaying the second conductive element is followed by forming a cap layer over the second conductive element and the second precursor.

23. The method claimed in claim 14, wherein said inlaying is followed by removing the stop layer and forming a cap layer over the second conductive element and the second low-k dielectric matrix.

24. The method claimed in claim 14, wherein the first precursor and the second precursor comprise the same compounds.

25. A wiring network of an integrated circuit, comprising:

an integrated circuit substrate comprising a first conductive element;

a dual damascene conductive element contacting the first conductive element, the dual damascene conductive element having smooth walls; and

first and second layers of porous interlevel dielectric formed over the substrate and surrounding the smooth walls of the dual damascene conductive element, the first and second layers of porous interlevel dielectric being separated by a stop layer.

26. The wiring network claimed in claim 25, wherein the dual damascene conductive element comprises:

a bulk copper material; and

a continuous layer of barrier material surrounding the bulk copper material.