Dynamically adjusting sample density in a graphics system

• US 20030218614A1
• Filed: 03/06/2003
• Published: 11/27/2003
• Est. Priority Date: 03/12/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lavelle, Michael G., Mahan, Justin Michael
• Granted Patent: US 6,999,087 B2
• Time in Patent Office: Days
• US Class Current: 345/539
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 2340/0442 Handling or displaying different aspect ratios, or changing the aspect ratio
• CPC Class Codes: G09G 2340/0464 Positioning
• CPC Class Codes: G09G 2360/08 Power processing, i.e. workload management for processors involved in display operations, such as CPUs or GPUs
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/36 characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence

Abstract

A graphics system may include a frame buffer and a hardware accelerator. The frame buffer may include a sample buffer and a double-buffered display area. The hardware accelerator may be coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area. A host computer may be configured (e.g., by means of stored program instructions) to dynamically update programmable registers of the graphics system to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.

Claims

1. A graphics system comprising:

a frame buffer, wherein the frame buffer includes a sample buffer and a double-buffered display area;

a hardware accelerator coupled to the frame buffer, and configured (a) to receive primitives, (b) to generate samples for the primitives based on a dynamically adjustable sample density value, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area.

2. The graphics system of claim 1, wherein the hardware accelerator includes a frame buffer address unit configured to map fragment coordinates to memory addresses of the frame buffer, wherein the frame buffer address unit includes dynamically programmable registers which control the mapping between fragment addresses and memory addresses.

3. The graphics system of claim 2, wherein a program executing on a host computer is configured to dynamically update the programmable registers to reallocate the sample buffer in the frame buffer in response to user input specifying a change in one or more window size parameters.

4. The graphics system of claim 3, wherein the program reallocates the sample buffer so as to achieve a maximum sample density.

5. The graphics system of claim 1, wherein memory devices in the frame buffer memory have parallel read and write busses, wherein the hardware accelerator is configured to perform (d) in parallel with a clear operation on source blocks in the sample buffer.

6. A method for controlling a graphics accelerator, wherein the graphics accelerator is configured to render samples into an available space of a frame buffer based on a programmable sample density, to filter the samples from the sample buffer into a double-buffered display area of the frame buffer, the method comprising:

(a) receiving input defining width and height of a window,

(b) computing a first number of memory allocation pages that cover the window horizontally based on the window width and a sample density estimate;

(c) computing a second number of memory allocation pages that cover the window vertically based on the window height and the sample density estimate;

(d) multiplying the first number and second number to determine a third number of memory allocation pages;

(e) performing (b), (c) and (d) one or more times to maximize the sample density estimate subject to the condition that the third number of memory allocation pages fit within the available space of the frame buffer;

(f) reprogramming the sample density of the graphics accelerator with maximized sample density estimate.

7. The method of claim 6, wherein the available space of the frame buffer is space in the frame buffer not occupied by the double-buffered display area.

8. A graphics system comprising:

a hardware accelerator;

a frame buffer coupled to the hardware accelerator, wherein the frame buffer includes a sample buffer and a double-buffered display area;

wherein the hardware accelerator is configured (a) to receive primitives, (b) to generate samples for the primitives based on a programmable sample density value which is dynamically adjustable, (c) to write the samples into the sample buffer, (d) to read the samples from the sample buffer, (e) to filter the samples to generate pixels, (f) to store the pixels in a back buffer of the double-buffered display area.

9. The graphics system of claim 8, further comprising a video output processor configured to read pixels from a front buffer of the double-buffered display area, wherein the hardware accelerator and the video output processor are configured to execute a buffer swap of the front and back buffers of the double-buffered display area in response to a swap command from a host computer.

10. The graphics system of claim 9, wherein the frame buffer comprises a plurality of random access memory (RAM) devices, wherein the video output processor is coupled to a subset of the RAM devices, wherein the double-buffered display area of the frame buffer is allocated within the subset of RAM devices.

11. The graphics system of claim 10, wherein the hardware accelerator couples to each of said plurality of RAM devices, wherein a size of the sample buffer and page boundaries of the sample buffer are programmable.

12. The graphics system of claim 10, wherein the RAM devices of said plurality are dynamic random access memories.

13. The graphics system of claim 8, further comprising one or more processing units configured to execute stored microcode, wherein, in response to execution of the stored microcode, the one or more processing units are configured to perform transform and lighting operations on vertices of said primitives.

14. The graphics system of claim 8, wherein the hardware accelerator includes a set of programmable registers that determine the location and size of the sample buffer within the frame buffer.

15. A method comprising:

(a) receiving input defining width and height of an adjusted window;

(b) computing a first number of memory allocation pages that cover the adjusted window horizontally based on the adjusted window width and a sample density estimate;

(c) computing a second number of memory allocation pages that cover the adjusted window vertically based on the adjusted window height and the sample density estimate;

(d) multiplying the first number and second number to determine a third number of memory allocation pages;

(e) performing (b), (c) and (d) one or more times to maximize the sample density estimate, within a set of sample densities achievable by a graphics accelerator, subject to the condition that the third number of memory allocation pages is less than or equal to an amount of available page space;

(f) writing the maximized sample density to the graphics accelerator.

16. The method of claim 15 wherein the available page space amount is a difference between a page capacity of the frame buffer and a page utilization amount of a double-buffered display area of a frame buffer.

17. The method of claim 15 further comprising writing the maximized value of the first number and the second number to the graphics accelerator.

18. The method of claim 15 further comprising writing the maximized value of the third number to the graphics accelerator.

19. The method of claim 15 further comprising repeating (a), (b), (c), (d) and (e) each time a user adjusts an onscreen window.

20. The method of claim 15 further comprising the graphics accelerator:

rendering samples into the sample storage area based on the maximized sample density, and

filtering the samples from the sample storage area to generate displayable pixels and storing the displayable pixels into a double-buffered display area of a frame buffer.

21. The method of claim 20, wherein the available page space amount equals a difference between a capacity of the frame buffer and a size of the double-buffered display area.

22. The method of claim 20, further comprising reading and displaying the displayable pixels from the double-buffered display area.

23. The method of claim 15, wherein the memory allocation pages have a page width and page height in pixels that depends on the sample density estimate.

24. The method of claim 15, wherein (a) through (e) are performed by a host computer coupled to the graphics accelerator through a host bus.