Nonvolatile memory device utilizing spin-valve-type designs and current pulses

• US 20030218903A1
• Filed: 05/24/2002
• Published: 11/27/2003
• Est. Priority Date: 05/24/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines SA (International Business Machines Corporation)
• Inventors: Luo, Jih-Shiuan
• Granted Patent: US 6,879,512 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods

Abstract

A memory device includes a plurality of memory elements each having: an antiferromagnetic layer, a first pinned layer coupled to the antiferromagnetic layer, a nonmagnetic spacer layer coupled to the first pinned layer, a second pinned layer coupled to the spacer, and a free layer coupled to the second pinned layer. A plurality of single wiring circuits are provided, each wiring circuit being coupled to a memory element. An addressing mechanism applies current pulses to the memory elements via the single wiring circuits for writing to the memory elements. The addressing mechanism also applies a sense current to the memory elements via the single wiring circuits for reading the memory elements.

Claims

1. A memory device, comprising:

an array of memory elements, each memory element having a free layer and a pinned layer, the pinned layer being settable to a magnetic orientation upon application of a current pulse thereto;

wherein a positive current pulse applied to the memory element sets the pinned layer to a first magnetic orientation representing a first binary state;

wherein a negative current pulse applied to the memory element sets the pinned layer to a second magnetic orientation representing a second binary state;

wherein a binary state of each memory element is read by applying a sense current to the memory element for determining a resistance of the memory element and determining the binary state based on the resistance.

2. The memory device as recited in claim 1, wherein the spin valve includes a second pinned layer.

3. The memory device as recited in claim 2, wherein the magnetic orientation of the second pinned layer orients itself based upon an orientation of the pinned layer.

4. The memory device as recited in claim 3, wherein the magnetic orientations of the pinned layers are oriented antiparallel.

5. The memory device as recited in claim 2, wherein an external magnetic field is applied to the array of memory elements for rotating the free layer during application of the sense current.

6. The memory device as recited in claim 1, wherein the current pulse and the sense current are applied to each memory element via the same electrical connection.

7. The memory device as recited in claim 1, wherein each current pulse has a duration of less than 200 nanoseconds.

8. The memory device as recited in claim 1, wherein each current pulse has a duration of less than 10 nanoseconds.

9. The memory device as recited in claim 1, wherein the magnetic orientation of the pinned layer is held in place by an antiferromagnetic layer, wherein the current pulse generates heat, wherein the pinned layer is heated to above a blocking temperature of the antiferromagnetic layer.

10. The memory device as recited in claim 1, wherein the array of memory elements is constructed by semiconductor deposition.

11. The memory device as recited in claim 1, wherein the pinned layer is self-pinned.

12. A memory device, comprising:

a plurality of memory elements each having;

an antiferromagnetic layer;

a first pinned layer coupled to the antiferromagnetic layer;

a nonmagnetic spacer layer coupled to the first pinned layer;

a second pinned layer coupled to the spacer; and

a free layer coupled to the second pinned layer;

a plurality of single wiring circuits, each wiring circuit being coupled to a memory element; and

an addressing mechanism for applying current pulses to the memory elements via the single wiring circuits for writing to the memory elements, the addressing mechanism also applying a sense current to the memory elements via the single wiring circuits for reading the memory elements.

13. The memory device as recited in claim 12, wherein a positive current pulse applied to the memory element sets the pinned layer to a first magnetic orientation representing a first binary state, wherein a negative current pulse applied to the memory element sets the pinned layer to a second magnetic orientation representing a second binary state.

14. The memory device as recited in claim 12, wherein the sense current is used to determine a resistance of a memory element, wherein a binary state of the memory element is determined based on the resistance.

15. The memory device as recited in claim 12, wherein the spacer layer is dimensioned such that the magnetic orientations of the first pinned layer and the second pinned layer are normally antiparallel each other.

16. The memory device as recited in claim 12, wherein, for each memory element:

the magnetic orientation of the pinned layer is held in place by an antiferromagnetic layer, wherein the current pulse generates heat, wherein the pinned layer is heated to above a blocking temperature of the antiferromagnetic layer.

17. A method for storing data, comprising:

applying a current pulse to each of a plurality of memory elements, each memory element having a free layer and a pinned layer, wherein a positive current pulse sets the pinned layer to a first magnetic orientation that represents a first binary state, wherein a negative current pulse sets the pinned layer to a second magnetic orientation that represents a second binary state;

applying a sense current to the memory elements;

measuring the resistance of each memory element; and

determining the binary state of each memory element based on the resistance.

18. The method as recited in claim 17, wherein the current pulse and the sense current are applied to each memory element via the same electrical connection.

19. The method as recited in claim 17, wherein the magnetic orientation of the pinned layer is held in place by an antiferromagnetic layer, wherein the current pulse generates heat, wherein the pinned layer is heated to above a blocking temperature of the antiferromagnetic layer.