Configurable stream processor apparatus and methods

• US 20030221086A1
• Filed: 02/13/2003
• Published: 11/27/2003
• Est. Priority Date: 02/13/2002
• Status: Abandoned Application

• Current Assignee: Dotcast Incorporated
• Original Assignee: Dotcast Incorporated
• Inventors: Radivojevic, Ivan P., Simovich, Slobodan A., Ramberg, Erik
• Application Number:
  US10/367,512
• Publication Number:
  US 20030221086A1
• Time in Patent Office: Days
• US Class Current: 712/4
• CPC Class Codes: G06F 15/8061 Details on data memory access

Abstract

Data processing apparatus and methods capable of executing vector instructions. Such apparatus preferably include a number of data buffers whose sizes are configurable in hardware and/or in software; a number of buffer control units adapted to control access to the data buffers, at lease one buffer control unit including at least one programmable write pointer register, read pointer register, read stride register and vector length register; a number of execution units for executing vector instructions using input operands stored in data buffers and storing produced results to data buffers; and at least one Direct Memory Access channel transferring data to and from said buffers. Preferably, at least some of the data buffers are implemented in dual-ported fashion in order to allow at least two simultaneous accesses per buffer, including at least one read access and one write access. Such apparatus and methods are advantageous, among other reasons, because they allow: (a) flexibility and simplicity of low-cost general-purpose RISC processors, (b) vector instructions to achieve high throughput on scientific real-time applications, and (c) configurable hardware buffers coupled with programmable Direct Memory Access (DMA) channels to enable the overlapping of data I/O and internal computations.

Claims

1. Data processing apparatus capable of executing vector instructions, comprising:

a. a plurality of data buffers whose sizes are configurable in hardware and/or in software;

b. a plurality of buffer control units adapted to control access to said data buffers, at least one buffer control unit including at least one programmable write pointer register, read pointer register, read stride register and vector length register;

c. a plurality of execution units for executing vector instructions using input operands stored in data buffers and storing produced results to data buffers;

d. at least one Direct Memory Access channel transferring data to and from said buffers; and

e. wherein at least some of said data buffers are implemented in dual-ported fashion in order to allow at least two simultaneous accesses per buffer, including at least one read access and one write access.

2. Data processing apparatus according to claim 1 wherein, for said at least one buffer control unit:

a. said write pointer register is adapted to be automatically incremented on each data buffer write access via either a vector instruction or DMA transfer;

b. said read pointer register is adapted to automatically be incremented or decremented on each data buffer read access via a vector instruction;

c. said read pointer register is adapted to be automatically incremented on each data buffer read access via DMA transfer;

d. said read stride register is adapted to be assigned per buffer control unit, such that at the end of a vector instruction, a read pointer corresponding to a vector instruction'"'"'s input operand(s) is automatically updated by assigning to it a new value equal to a value of the read pointer before the vector instruction execution, incremented by a value contained in the read stride register; and

e. said vector length register is adapted to indicate the number of vector elements to be processed by a vector instruction.

3. Data processing apparatus according to claim 1 wherein:

a. the effective range of at least some of said read and write pointer registers used in buffer addressing is equal to the active buffer size; and

b. address generation arithmetic on contents of read and write pointer registers is performed modulo buffer size.

4. Data processing apparatus according to claim 2 wherein:

a. the effective range of at least some of said read and write pointer registers used in buffer addressing is equal to the active buffer size; and

b. address generation arithmetic on contents of read and write pointer registers is performed modulo buffer size.

5. Data processing apparatus according to claim 1 wherein a plurality of data buffers whose sizes are configurable in hardware are so configurable using a plurality of external pins.

6. Data processing apparatus according to claim 1 wherein a plurality of data buffers whose sizes are configurable in software are so configurable using control registers.

7. Data processing apparatus capable of executing vector instructions, comprising:

a. a plurality of data buffers whose sizes are configurable in hardware and/or in software;

b. a plurality of buffer control units adapted to control access to said data buffers, at lease one buffer control unit including at least one programmable write pointer register, read pointer register, read stride register and vector length register;

c. a plurality of execution units for executing vector instructions using input operands stored in data buffers and storing produced results to data buffers;

d. at least one Direct Memory Access channel transferring data to and from said buffers; and

e. wherein at least some of said data buffers are implemented in dual-ported fashion in order to allow at least two simultaneous accesses per buffer, including at least one read access and one write access;

wherein, for said at least one buffer control unit;

f. said write pointer register is adapted to be automatically incremented on each data buffer write access via either a vector instruction or DMA transfer;

g. said read pointer register is adapted to automatically be incremented or decremented on each data buffer read access via a vector instruction;

h. said read pointer register is adapted to be automatically incremented on each data buffer read access via DMA transfer;

i. said read stride register is adapted to be assigned per buffer control unit, such that at the end of a vector instruction, a read pointer corresponding to a vector instruction'"'"'s input operand(s) is automatically updated by assigning to it a new value equal to a value of the read pointer before the vector instruction execution, incremented by a value contained in the read stride register; and

j. said vector length register is adapted to indicate the number of vector elements to be processed by a vector instruction.

8. Data processing apparatus according to claim 7 wherein:

a. the effective range of at least some of said read and write pointer registers used in buffer addressing is equal to the active buffer size; and

b. address generation arithmetic on contents of read and write pointer registers is performed modulo buffer size.

9. A method of data processing, comprising:

a. providing data processing apparatus capable of executing vector instructions, said apparatus comprising;

1. a plurality of data buffers whose sizes are configurable in hardware and/or in software;

2. a plurality of buffer control units adapted to control access to said data buffers, at lease one buffer control unit including at least one programmable write pointer register, read pointer register, read stride register and vector length register;

3. a plurality of execution units for executing vector instructions using input operands stored in data buffers and storing produced results to data buffers;

4. at least one Direct Memory Access channel transferring data to and from said buffers; and

5. wherein at least some of said data buffers are implemented in dual-ported fashion in order to allow at least two simultaneous accesses per buffer, including at least one read access and one write access;

b. accessing a plurality of source data buffers, each containing at least one input operand array in response to one said vector instruction;

c. detecting, before execution of a vector instruction, whether there is at least one input operand element in each of the source buffers; and

d. prohibiting execution of the vector instruction if any of said source buffers is empty.

10. A method of data processing, comprising:

a. providing data processing apparatus capable of executing vector instructions, said apparatus comprising;

1. a plurality of data buffers whose sizes are configurable in hardware and/or in software;

2. a plurality of buffer control units adapted to control access to said data buffers, at lease one buffer control unit including at least one programmable write pointer register, read pointer register, read stride register and vector length register;

3. a plurality of execution units for executing vector instructions using input operands stored in data buffers and storing produced results to data buffers;

4. at least one Direct Memory Access channel transferring data to and from said buffers; and

5. wherein at least some of said data buffers are implemented in dual-ported fashion in order to allow at least two simultaneous accesses per buffer, including at least one read access and one write access;

b. accessing at least one source data buffer which includes at least one input operand array to be transferred via said direct memory access channel;

c. detecting, before execution of said direct memory access transfer, whether there is at least one input operand element in a said source buffer; and

d. prohibiting execution of said direct memory access transfer if said source buffer is empty.