Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same

• US 20030222311A1
• Filed: 11/13/2002
• Published: 12/04/2003
• Est. Priority Date: 05/28/2002
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Granted Patent: US 6,922,217 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: G02F 2201/50 Protective arrangements
• CPC Class Codes: G02F 2202/103 a-Si
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate

Abstract

In an amorphous silicon thin film transistor-liquid crystal display device and a method of manufacturing the same, gate patterns including a gate line and a gate electrode are formed on an insulation substrate having a display region and a driving circuit region on which a plurality of shift registers are formed, a gate insulating film, active layer patterns and data patterns including source and drain electrodes are formed successively on the substrate, a passivation layer on the substrate has a first contact hole exposing a drain electrode of the display region and second and third contact holes respectively exposing a gate electrode and source and drain electrodes of a first transistor of each of the shift registers, an electrode patterns on the passivation layer include a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode to the source and drain electrodes of the first transistor through the second and third contact holes, and the gate driving circuit including the shift registers and the wirings are integrated on the insulating substrate without an additional process, thereby simplifying the manufacturing process.

Claims

1. An amorphous silicon thin film transistor-liquid crystal display device comprising:

an insulating substrate including a display region on which a pixel array is formed and a driving circuit region on which a plurality of shift registers are formed;

gate patterns formed on the substrate, the gate patterns including a gate line and a gate electrode;

a gate insulating film formed on the substrate including the gate patterns;

active layer patterns formed on the gate insulating film;

data patterns formed on the substrate and the active layer patterns, the data patterns including a source electrode making contact with a first region of the active layer pattern, a drain electrode making contact with a second region of the active layer pattern and a data line connected to the drain electrode;

a passivation layer formed on the substrate including the data patterns, the passivation layer having a first contact hole exposing a drain electrode of the display region, a second contact hole exposing a gate electrode of a first transistor of each of the shift registers and a third contact hole exposing source and drain electrodes of the first transistor; and

electrode patterns formed on the passivation layer and including a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode and the source and drain electrodes of the first transistor through the second and third contact holes.

2. The device as claimed in claim 1, further comprising main wirings disposed on the substrate of the driving circuit region for applying signals to each of the shift registers, the main wirings of the shift registers formed from a single layer.

3. The device as claimed in claim 2, further comprising branch wirings disposed on the substrate of the driving circuit region and crossing the main wirings to connect the main wirings to a transistor of each shift register in the driving circuit region.

4. The device as claimed in claim 3, wherein a portion of the branch wirings where the branch wiring and main wiring cross each other have a line width narrower than that of the main wiring.

5. The device as claimed in claim 3, wherein the main wirings are formed from a different layer from the branch layer.

6. The device as claimed in claim 5, wherein the main wirings are formed from a same layer as in the gate patterns, while the branch wirings are formed from a same layer as in the data patterns.

7. The device as claimed in claim 5, wherein the main wirings are formed from a same layer as in the data patterns, while the branch wirings are formed from a same layer as in the gate patterns.

8. The device as claimed in claim 3, wherein the electrode patterns further include a third electrode connecting one of the main wirings and one of the branch wirings through a forth contact hole formed on one of the main wirings and a fifth contact hole formed on one of the branch wirings.

9. The device as claimed in claim 8, wherein the forth and fifth contact holes have a larger size than the line width of the branch wirings.

10. The device as claimed in claim 1, wherein a gate electrode of a driving transistor in the driving circuit region has a box structure and source and drain electrodes thereof have an interdigital structure.

11. The device as claimed in claim 1, further comprising a capacitor lower electrode formed on the substrate of the display region and spaced apart from the gate line in parallel, the capacitor lower electrode formed from a same layer as in the gate patterns.

12. An amorphous silicon thin film transistor-liquid crystal display device comprising:

an insulating substrate including a display region on which a plurality of gate lines and a plurality of data lines are formed, and a gate driving circuit region;

a plurality of shift registers formed on the substrate of the gate driving circuit region, the shift registers including a number of thin film transistors having a gate electrode and source and drain electrodes, the shift registers for selecting a plurality of the gate lines successively;

main wirings disposed on the substrate of the gate driving circuit region for applying signals to each of the shift registers, the main wirings of the shift registers formed from a single layer;

a passivation layer formed on the substrate including the shift registers and the main wirings, the passivation layer having a first contact hole exposing a portion of the data line of the display region, a second contact hole exposing a gate electrode of a first transistor of each of the shift registers and a third contact hole exposing source and drain electrodes of the first transistor; and

electrode patterns formed on the passivation layer, the electrode patterns including a first electrode connected to the data line of the display region through the first contact hole and a second electrode connecting the gate electrode and the source and drain electrodes of the first transistor through the second and third contact holes.

13. The device as claimed in claim 12, further comprising branch wirings disposed on the substrate of the driving circuit region and crossing the main wirings to connect the main wirings to the transistors of each of the shift registers.

14. The device as claimed in claim 13, wherein a portion of the branch wirings where the branch wirings and the main wirings cross each other have a line width narrower than that of the main wirings.

15. The device as claimed in claim 13, wherein the main wirings are formed from a different layer from the branch layer.

16. The device as claimed in claim 15, wherein the main wirings are formed from a same layer as in the gate line, while the branch wiring is formed from a same layer as in the data line.

17. The device as claimed in claim 15, wherein the main wirings are formed from a same layer as the data line, while the branch wiring is formed from a same layer as in the gate line.

18. The device as claimed in claim 13, wherein the electrode patterns further include a third electrode connecting one of the main wirings to one of the branch wirings through a fourth contact hole formed on one of the main wirings and a fifth contact hole formed on one of the branch wirings.

19. The device as claimed in claim 18, wherein the forth and fifth contact holes have a larger size than the line width of the branch wirings.

20. The device as claimed in claim 12, wherein a gate electrode of a driving transistor in the driving circuit region has a box structure and source and drain electrodes thereof have an interdigital structure.

21. A method of manufacturing an amorphous silicon thin film transistor-liquid crystal display device comprising steps of:

forming gate patterns including gate lines and gate electrodes on an insulating substrate having a display region on which a pixel array is formed and a driving circuit region on which a plurality of shift registers are formed;

forming a gate insulating film on the substrate having the gate patterns;

forming active layer patterns on the gate insulating film over the gate electrodes;

forming data patterns on the substrate and the active layer patterns, the data patterns including a source electrode making contact with a first region of the active layer pattern, a drain electrode making contact with a second region of the active layer pattern and a data line connected to the drain electrode;

forming a passivation layer on the substrate including the data patterns;

etching the passivation layer and the gate insulating film to form a first contact hole exposing a drain electrode of the display region, a second contact hole exposing a gate electrode of a first transistor of each of the shift registers, and a third contact hole exposing source and drain electrodes of the first transistor; and

forming electrode patterns on the passivation layer, the electrode patterns including a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode to source and drain electrodes of the first transistor through the second and third contact holes.

22. The method as claimed in claim 21, wherein main wirings that are made from a same layer as the gate pattern or the data pattern are formed on the substrate of the driving circuit region and formed from the same layer from a first shift register to a last shift register, in the step of forming the gate patterns or the step of forming the data patterns.

23. The method as claimed in of claim 22, wherein branch wirings comprised of a same layer as in the data pattern or the gate pattern are formed on the substrate of the driving circuit region and formed crossing the main wirings so as to connect the main wirings to the transistors of the shift registers, in the step of forming the data patterns or the step of forming the gate patterns.

24. The method as claimed in claim 23, wherein a portion of the branch wirings where the branch wiring and the main wiring cross each other have a line width narrower than that of the main wirings.

25. The method as claimed in claim 23, wherein a forth contact hole exposing a portion of the main wiring and a fifth contact hole exposing a portion of the branch wiring are formed in the step of forming the first, second and third contact holes, and the electrode patterns further include a third electrode connecting one of the main wiring to one of the branch wirings through the forth and fifth contact holes.

26. The method as claimed in claim 25, wherein the forth and fifth contact holes have a larger size than the line width of the branch wiring.

27. The method as claimed in claim 21, wherein a capacitor lower electrode is formed on the substrate of the display region and is spaced apart from the gate line in parallel in the step of forming the gate patterns, the capacitor lower electrode being formed from a single layer as in the gate patterns.

28. The method as claimed in claim 21, wherein a gate electrode of a driving transistor in the driving circuit region has a box structure and source and drain electrodes thereof have an interdigital structure.

29. A method of manufacturing an amorphous silicon thin film transistor-liquid crystal display device comprising steps of:

forming gate patterns including gate lines and gate electrodes on an insulating substrate having a display region on which a pixel array is formed and a driving circuit region on which a plurality of shift registers are formed;

forming a gate insulating film on the substrate including the gate patterns;

forming active layer patterns and data patterns on the gate insulating film using one mask, the data patterns including a source electrode making contact with a first region of the active layer pattern, a drain electrode making contact with a second region of the active layer pattern and a data line connected to the drain electrode;

forming a passivation layer on the substrate including the data patterns;

etching the passivation layer and the gate insulating film to form a first contact hole exposing the drain electrode of the display region, a second contact hole exposing a gate electrode of a first transistor of each of the shift registers, and a third contact hole exposing source and drain electrodes of the first transistor; and

forming electrode patterns on the passivation layer, the electrode patterns including a first electrode connected to the drain electrode of the display region through the first contact hole and a second electrode connecting the gate electrode and source and drain electrodes of the first transistor through the second and third contact holes.

30. The method as claimed in claim 29, wherein main wirings comprised of a same layer as in the gate pattern or the data pattern are formed on the substrate of the driving circuit region and formed of a same layer from a first shift register to a last shift register, in the step of forming the gate patterns or the step of forming the data patterns.

31. The method as claimed in of claim 29, wherein branch wirings comprised of a same layer as in the data patterns or the gate patterns are formed on the substrate of the driving circuit region and formed crossing the main wirings so as to connect the main wirings to the transistors of each of the shift registers, in the step of forming the data patterns or the step of forming the gate patterns.

32. The method as claimed in claim 31, wherein a portion of the branch wirings where the branch wirings and the main wirings cross each other have a line width narrower than that of the main wirings.

33. The method as claimed in claim 31, wherein a forth contact hole exposing a portion of the main wiring and a fifth contact hole exposing a portion of the branch wiring are formed in the step of forming the first, second and third contact holes, and the electrode patterns further include a third electrode connecting one of the main wirings to one of the branch wirings through the forth and fifth contact holes.

34. The method as claimed in claim 33, wherein the forth and fifth contact holes have a larger size than the line width of the branch wirings.

35. The method as claimed in claim 29, wherein the step of forming active layer patterns and the data patterns using one mask is comprised of the steps of:

successively depositing an amorphous silicon layer, an impurity-doped amorphous silicon layer and a metal layer;

forming a photosensitive film pattern on the metal layer such that a height of a channel portion between the source electrode and the drain electrode is lower than a surface height of the source and drain electrodes; and

patterning the exposed metal layer and the underlying doped amorphous silicon layer and amorphous silicon layer using the photosensitive film pattern as a mask, to thereby form the active layer patterns and the data patterns.

36. The method as claimed in claim 29, wherein a capacitor lower electrode is formed on the substrate of the display region and spaced apart from the gate line in parallel in the step of forming the gate patterns, the capacitor lower electrode being formed of a same layer as in the gate pattern.

37. The method as claimed in claim 29, wherein a gate electrode of a driving transistor in the driving circuit region has a box structure and source and drain electrodes of the driving transistor have an interdigital structure.