BACKPLANES FOR DISPLAY APPLICATIONS, AND COMPONENTS FOR USE THEREIN

• US 20030222315A1
• Filed: 04/24/2003
• Published: 12/04/2003
• Est. Priority Date: 04/24/2002
• Status: Active Grant

• Current Assignee: E Ink Corporation (E Ink Holdings Incorporated)
• Original Assignee: E Ink Corporation (E Ink Holdings Incorporated)
• Inventors: Drzaic, Paul S., Chen, Yu, Kazlas, Peter T., Ritenour, Andrew P., Amundson, Karl R., Denis, Kevin L.
• Granted Patent: US 7,116,318 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/344 based on particles moving in a fluid or in a gas, e.g. electrophoretic devices electrophoretic devices per se G02F1/167
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor

Abstract

A thin-film transistor includes a gate electrode having a first gate electrode edge and a second gate electrode edge opposite the first gate electrode edge. The TFT also includes a drain electrode having a first drain electrode edge that overlaps the first gate electrode edge, and a second drain electrode edge that overlaps the second gate electrode edge. A method for fabricating a diode array for use in a display includes deposition of a conductive layer adjacent to a substrate, deposition of a doped semiconductor layer adjacent to the substrate, and deposition of an undoped semiconductor layer adjacent to the substrate. A display pixel unit provides reduced capacitative coupling between a pixel electrode and a source line. The unit includes a transistor, the pixel electrode, and the source line. The source line includes an extension that provides a source for the transistor. A patterned conductive portion is disposed adjacent to the source line. Another display pixel unit provides reduced pixel electrode voltage shifts. The unit includes a transistor, a pixel electrode, a source line and a balance line. The invention also provides a driver for driving a display provided with such a balance line.

Claims

1. A transistor comprising a source electrode, a drain electrode spaced from the source electrode by a channel, a semiconductor layer extending across the channel, and a gate electrode disposed adjacent the channel such that application of a voltage to the gate electrode will vary the conductivity of the semiconductor layer extending across the channel, the gate electrode having a first gate electrode edge and a second gate electrode edge spaced from the first gate electrode edge, the drain electrode having a first drain electrode edge portion which overlaps the first gate electrode edge to define a first overlap area, the drain electrode also having a second drain electrode edge portion which overlaps the second gate electrode edge to define a second overlap area, such that translation of the gate electrode relative to the drain electrode in a direction which increases the first overlap area will decrease the second overlap area, or vice versa.

2. A transistor according to claim 1 which is a thin film transistor wherein the source electrode, the drain electrode, the gate electrode and the semiconductor layer have the form of thin layers deposited upon a substrate.

3. A transistor according to claim 1 wherein the gate electrode comprises a base portion and first and second projections extending in one direction away from the base portion and substantially parallel to each other, and the first and second gate electrode edges are formed by the edges of the first and second projections respectively facing away from the other of said projections.

4. A transistor according to claim 3 wherein the source electrode extends between the first and second projections and overlaps the inward edges of each of these projections.

5. A transistor according to claim 1 wherein the gate electrode has the form of a polygon having a central aperture, a central portion of the drain electrode overlaps at least part of said central aperture, and the first and second overlap areas are formed by overlap between the drain electrode and portions of the gate electrode adjacent said central aperture.

6. A transistor according to claim 5 wherein said central aperture has two straight edges on opposed sides of the aperture, said straight edges forming the first and second gate electrode edges.

7. A transistor according to claim 1 further comprising a capacitor electrode overlapping part of the drain electrode, and a dielectric layer disposed between the capacitor electrode and the drain electrode so that the capacitor electrode and the drain electrode together form a capacitor.

8. A transistor according to claim 7 wherein the gate electrode has substantially the form of a polygon having a central aperture, a central portion of the drain electrode overlaps at least part of said central aperture, and the first and second overlap areas are formed by overlap between the drain electrode and portions of the gate electrode adjacent said central aperture, and wherein the capacitor electrode is disposed within the central aperture and is connected to a capacitor electrode line by a conductor passing through a gap in the gate electrode.

9. A transistor according to claim 1 further comprising a pixel electrode connected to the drain electrode.

10. A transistor according to claim 9 further comprising a layer of dielectric disposed between the drain electrode and the pixel electrode, and a conductive via extending from the drain electrode to the pixel electrode through the layer of dielectric.

11. A transistor according to claim 10 wherein the pixel electrode overlies both the gate and drain electrodes.

12. A backplane for an electro-optic display, the backplane comprising a substrate and at least one transistor according to claim 1.

13. An electro-optic display comprising a backplane according to claim 12, a layer of electro-optic medium disposed on the backplane and covering the at least one transistor, and a front electrode disposed on the opposed side of the layer of electro-optic medium from the substrate and the at least one transistor.

14. An electro-optic display according to claim 13 wherein the electro-optic medium is a rotating bichromal member or electrochromic medium.

15. An electro-optic display according to claim 13 wherein the electro-optic medium is an electrophoretic medium.

16. An electro-optic display according to claim 15 wherein the electro-optic medium is an encapsulated electrophoretic medium.

17. A process for forming a plurality of diodes on a substrate, the process comprising:

depositing a conductive layer on the substrate;

depositing a first doped semiconductor layer on the substrate over the conductive layer;

patterning the conductive layer and the doped semiconductor layer to form a plurality of discrete conductive layer/first doped semiconductor layer areas;

depositing an undoped semiconductor layer on the substrate over the plurality of discrete conductive layer/first doped semiconductor layer areas;

forming a plurality of second doped semiconductor layer areas on the opposed side of the undoped semiconductor layer from the plurality of discrete conductive layer/first doped semiconductor layer areas,

whereby the plurality of discrete conductive layer/first doped semiconductor layer areas, the undoped semiconductor layer and the plurality of second doped semiconductor layer areas form a plurality of diodes on the substrate.

18. A process according to claim 17 wherein the patterning step is effected by lithography.

19. A process according to claim 17 wherein the undoped semiconductor layer is not patterned so that this layer extends continuously between adjacent diodes.

20. A process according to claim 17 wherein the first doped semiconductor layer is formed of n-doped amorphous silicon.

21. A process according to claim 17 wherein the undoped semiconductor layer is formed of amorphous silicon.

22. A process according to claim 17 wherein the plurality of second doped semiconductor layer areas are formed of n-doped amorphous silicon.

23. A process according to claim 17 wherein the plurality of second doped semiconductor layer areas are formed by first depositing a continuous second doped semiconductor layer and thereafter patterning this layer to form the plurality of second doped semiconductor layer areas.

24. A process according to claim 23 wherein, after deposition of the continuous second doped semiconductor layer, a continuous second conductive layer is deposited over the second doped semiconductor layer and both the second doped semiconductor layer and the second conductive layer are patterned in a single patterning step.

25. A process according to claim 23 wherein, after deposition of the continuous second doped semiconductor layer, a patterned second conductive layer is deposited over the second doped semiconductor layer and the patterned second conductive layer is thereafter used as an etch mask for patterning of the second doped semiconductor layer.

26. A process according to claim 17 wherein the plurality of second doped semiconductor layer areas are formed by printing.

27. A process for forming a diode on a substrate, the process comprising:

depositing a doped semiconductor layer on the substrate;

forming two spaced areas of undoped semiconductor material on the opposed side of the doped semiconductor layer from the substrate; and

forming two spaced areas of conductive material, each of said areas being in contact with one of the areas of undoped semiconductor material on the opposed side thereof from the doped semiconductor layer.

28. A process according to claim 27 wherein the two spaced areas of undoped semiconductor material and the two spaced areas of conductive material are formed by depositing continuous layers of undoped semiconductor material and conductive material and thereafter patterning both these continuous layers to form said spaced areas.

29. A process according to claim 28 wherein the patterning of the continuous layers of undoped semiconductor material and conductive material is effected in a single lithography patterning step.

30. A process according to claim 27 wherein the two spaced areas of undoped semiconductor material and the two spaced areas of conductive material are formed by depositing a continuous layer of undoped semiconductor material, forming the two spaced areas of conductive material, and thereafter using the two spaced areas of conductive material as an etch mask for patterning of the continuous layer of undoped semiconductor material to form the two spaced areas of undoped semiconductor material.

31. A process according to claim 27 wherein the doped semiconductor layer is formed of n-doped amorphous silicon.

32. A process according to claim 27 wherein the undoped semiconductor material is amorphous silicon.

33. A backplane for an electro-optic display, the backplane comprising a source line, a transistor and a pixel electrode connected to the source line via the transistor, the pixel electrode extending over part of the source line to form an overlap area, the backplane further comprising a conductive portion disposed between the source line and the pixel electrode, said conductive portion reducing the source line/pixel electrode capacitance.

34. A backplane according to claim 33 wherein the conductive portion extends over at least about 30 percent of the overlap area.

35. A backplane according to claim 33 wherein the conductive portion extends over at least about 80 percent of the overlap area.

36. A backplane according to claim 33 wherein the conductive portion extends over at least about 90 percent of the overlap area.

37. A backplane according to claim 33 further comprising a capacitor electrode which forms a capacitor with at least one of the pixel electrode and the electrode of the transistor connected directly to the pixel electrode, the conductive portion being connected to the capacitor electrode.

38. A backplane according to claim 37 wherein the drain electrode of the transistor is connected to the pixel electrode, the backplane further comprising a layer of dielectric disposed between the drain electrode and the pixel electrode, and a conductive via extending from the drain electrode to the pixel electrode through the layer of dielectric, the capacitor electrode forming the capacitor with the drain electrode.

39. An electro-optic display comprising a backplane according to claim 33, a layer of electro-optic medium disposed on the backplane and covering the pixel electrode, and a front electrode disposed on the opposed side of the layer of electro-optic medium from the pixel electrode.

40. An electro-optic display according to claim 39 wherein the electro-optic medium is a rotating bichromal member or electrochromic medium.

41. An electro-optic display according to claim 39 wherein the electro-optic medium is an electrophoretic medium.

42. An electro-optic display according to claim 41 wherein the electro-optic medium is an encapsulated electrophoretic medium.

43. A backplane for an electro-optic display, the backplane comprising a source line, a transistor and a pixel electrode connected to the source line via the transistor, the pixel electrode lying adjacent part of the source line so as to provide a source line/pixel electrode capacitance, the backplane further comprising a balance line at least part of which is disposed adjacent the pixel electrode so as to provide a balance line/pixel electrode capacitance, and voltage supply means for applying to the balance line a voltage opposite in polarity to that applied to the source line.

44. A backplane according to claim 43 wherein the balance line extends substantially parallel to the source line.

45. A backplane according to claim 43 wherein the balance line has substantially the same shape as the source line.

46. A backplane according to claim 43 wherein the balance line has a shape which is substantially a mirror image of the shape of the source line.

47. A backplane according to claim 43 wherein the balance line is wider than the source line.

48. A backplane according to claim 43 wherein the absolute value of the product of the balance line/pixel electrode capacitance and the voltage applied to the balance line by the voltage supply means is at least about 50 percent of the absolute value of the product of the source line/pixel electrode capacitance and the voltage applied to the source line.

49. A backplane according to claim 48 wherein the absolute value of the product of the balance line/pixel electrode capacitance and the voltage applied to the balance line by the voltage supply means is at least about 90 percent of the absolute value of the product of the source line/pixel electrode capacitance and the voltage applied to the source line.

50. A backplane according to claim 49 wherein the absolute value of the product of the balance line/pixel electrode capacitance and the voltage applied to the balance line by the voltage supply means is substantially equal to the absolute value of the product of the source line/pixel electrode capacitance and the voltage applied to the source line.

51. A backplane according to claim 50 wherein the balance line/pixel electrode capacitance is N times the source line/pixel electrode capacitance, where N is greater than 1, and the voltage supply means applies to the balance line a voltage of substantially—

1/N times the voltage applied to the source line.

52. A backplane according to claim 43 wherein the pixel electrode overlies both the source line and the balance line.

53. A backplane according to claim 52 wherein the drain electrode of the transistor is connected to the pixel electrode, the backplane further comprising a layer of dielectric disposed between the drain electrode and the pixel electrode, and a conductive via extending from the drain electrode to the pixel electrode through the layer of dielectric.

54. A backplane according to claim 43 wherein the source line and the balance line are coplanar with the pixel electrode.

55. An electro-optic display comprising a backplane according to claim 43, a layer of electro-optic medium disposed on the backplane and covering the pixel electrode, and a front electrode disposed on the opposed side of the layer of electro-optic medium from the pixel electrode.

56. An electro-optic display according to claim 55 wherein the electro-optic medium is a rotating bichromal member or electrochromic medium.

57. An electro-optic display according to claim 55 wherein the electro-optic medium is an electrophoretic medium.

58. An electro-optic display according to claim 57 wherein the electro-optic medium is an encapsulated electrophoretic medium.

59. A driver for driving an electro-optic display having a source line and a balance line, the driver comprising:

a first input arranged to receive a digital signal representative of the magnitude of the voltage to be applied to the source line;

a second input arranged to receive a sign bit representative of the polarity of the voltage to be applied to the source line;

at least one digital/analogue converter;

a first output arranged to output a source line voltage the magnitude and polarity of which are determined by the signals received at the first and second inputs respectively; and

a second output arranged to output a balance line voltage of opposite polarity to the source line voltage, the magnitude of the balance line voltage bearing a predetermined relationship to the magnitude of the source line voltage.

60. A driver according to claim 59 having separate first and second digital/analogue converters, both the first and second digital/analogue converters being connected to both the first and second inputs.

61. A driver according to claim 60 wherein the first digital/analogue converter is connected to the first output and the second digital/analogue converter is connected to the second output.

62. A driver according to claim 60 wherein the first digital/analogue converter is a positive output digital/analogue converter and the second digital/analogue converter is a negative output digital/analogue converter, the driver further comprising a reversing switch having a first position in which the first digital/analogue converter is connected to the first output and the second digital/analogue converter is connected to the second output, and a second position in which the first digital/analogue converter is connected to the second output and the second digital/analogue converter is connected to the first output.

63. A driver according to claim 62 further comprising a first digital processor connected between the first input and the input of the first digital/analogue converter and a second digital processor connected between the first input and the input of the second digital/analogue converter.

64. A driver for driving an electro-optic display having a source line and a balance line, the driver comprising:

a first input arranged to receive a digital signal representative of the magnitude of the voltage to be applied to the source line;

a second input arranged to receive a sign bit representative of the polarity of the voltage to be applied to the source line;

a third input arranged to receive a digital signal representative of the magnitude of the voltage to be applied to the balance line;

a first positive output digital/analogue converter

a second negative output digital/analogue converter;

a first output arranged to output a source line voltage the magnitude and polarity of which are determined by the signals received at the first and second inputs respectively;

a second output arranged to output a balance line voltage of opposite polarity to the source line voltage, the magnitude of the balance line voltage being determined by the signal received at the third input a first reversing switch connected to the first and third inputs and the inputs of the first and second digital/analogue converters, the first reversing switch having a first position in which the first input is connected to the first digital/analogue converter and the third input is connected to the second digital/analogue converter, and a second position in which the first input is connected to the second digital/analogue converter and the third input is connected to the first digital/analogue converter; and

a second reversing switch connected to the outputs of the first and second digital/analogue converters and the first and second outputs, the second reversing switch having a first position in which the first digital/analogue converter is connected to the first output and the second digital/analogue converter is connected to the second output, and a second position in which the first digital/analogue converter is connected to the second output and the second digital/analogue converter is connected to the first output.