Active cascode differential latch

• US 20030222680A1
• Filed: 06/04/2002
• Published: 12/04/2003
• Est. Priority Date: 06/04/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jaussi, James E.
• Granted Patent: US 6,791,372 B2
• Time in Patent Office: Days
• US Class Current: 327/65
• CPC Class Codes: H03H 15/02 using analogue shift registers
• CPC Class Codes: H03H 15/023 with parallel-input configuration
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 3/35613 the input circuit having a differential configuration

Abstract

An active cascode differential latch for providing a logic output signal indicative of whether or not a first current is greater than a second current. The first and second currents are fed into two input ports of the active cascode differential latch. The active cascode differential latch has a relatively small input impedance, and has utility for comparators and discrete-time analog filters, to name just a few, particularly when used in high bandwidth and low voltage applications.

Claims

1. An active cascode differential latch comprising:

a first input port;

a second input port;

a first transistor of a first conductivity type comprising a gate, and a drain connected to the first input port;

a second transistor of the first conductivity type comprising a gate, and a drain connected to the second input port;

a first active cascode transistor of the first conductivity type comprising a source connected to the drain of the first transistor, and a gate connected to the gate of the first transistor;

a second active cascode transistor of the first conductivity type comprising a source connected to the drain of the second transistor, and a gate connected to the gate of the second transistor; and

a load coupled to the first and second active cascode transistors.

2. The active cascode transistor as set forth in claim 1, wherein the load comprises:

a third transistor of a second conductivity type, the second conductivity type complementary to the first conductivity type, comprising a drain connected to the drain of the first active cascode transistor, and a gate connected to the gate of the first active cascode transistor and the drain of the second cascode transistor; and

a fourth transistor of a second conductivity type comprising a drain connected to the drain of the second active cascode transistor, and a gate connected to the gate of the second active cascode transistor and the drain of the first cascode transistor.

3. The active cascode differential latch as set forth in claim 2, further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

4. The active cascode differential latch as set forth in claim 1, further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

5. An analog filter comprising a tap, the tap comprising:

a voltage-to-current converter comprising a first input port and a second input port, the voltage-to-current converter comprising;

a first drive transistor to conduct a first current I₁ and comprising a gate connected to the first input port;

a second drive transistor to conduct a second current I₂ and comprising a gate connected to the second input port; and

a current source to source a current I to the first and second drive transistors so that the sum of the first current I₁ and the second current I₂ is substantially equal to the current;

a current multiplier comprising first and second output ports, the current multiplier coupled to the voltage-to-current converter to pass a first weighted current α

I₁ to the first output port and a second weighted current α

I₂ to the second output port, where α

is a weight; and

an active cascode differential latch comprising;

a first input port connected to the first output port of the current multiplier;

a second input port connected to the second output port of the current multiplier;

a first transistor of a first conductivity type comprising a gate, and a drain connected to the first input port;

a second transistor of the first conductivity type comprising a gate, and a drain connected to the second input port;

a first active cascode transistor of the first conductivity type comprising a source connected to the drain of the first transistor, and a gate connected to the gate of the first transistor;

a second active cascode transistor of the first conductivity type comprising a source connected to the drain of the second transistor, and a gate connected to the gate of the second transistor; and

a load coupled to the first and second active cascode transistors.

6. The analog filter as set forth in claim 5, wherein the load comprises:

a third transistor of a second conductivity type, the second conductivity type complementary to the first conductivity type, comprising a drain connected to the drain of the first active cascode transistor, and a gate connected to the gate of the first active cascode transistor and the drain of the second cascode transistor; and

a fourth transistor of a second conductivity type comprising a drain connected to the drain of the second active cascode transistor, and a gate connected to the gate of the second active cascode transistor and the drain of the first cascode transistor.

7. The analog filer as set forth in claim 6, the active cascode differential latch further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

8. The analog filter as set forth in claim 5, the active cascode differential latch further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

9. A comparator comprising:

a differential pair of transistors to provide a first current and a second current in response to a differential voltage;

an active cascode differential latch comprising;

a first input port to receive the first current;

a second input port to receive the second current;

a first transistor of a first conductivity type comprising a gate, and a drain connected to the first input port;

a second transistor of the first conductivity type comprising a gate, and a drain connected to the second input port;

a first active cascode transistor of the first conductivity type comprising a source connected to the drain of the first transistor, and a gate connected to the gate of the first transistor;

a second active cascode transistor of the first conductivity type comprising a source connected to the drain of the second transistor, and a gate connected to the gate of the second transistor; and

a load coupled to the first and second active cascode transistors.

10. The comparator as set forth in claim 9, the load comprising:

a third transistor of a second conductivity type, the second conductivity type complementary to the first conductivity type, comprising a drain connected to the drain of the first active cascode transistor, and a gate connected to the gate of the first active cascode transistor and the drain of the second cascode transistor; and

a fourth transistor of a second conductivity type comprising a drain connected to the drain of the second active cascode transistor, and a gate connected to the gate of the second active cascode transistor and the drain of the first cascode transistor.

11. The comparator as set forth in claim 10, the active cascode differential latch further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

12. The comparator as set forth in claim 9, the active cascode differential latch further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

13. A computer system comprising:

a board comprising a first transmission line and a second transmission line; and

a receiver coupled to the first and second transmission lines, the receiver comprising an active cascode differential latch, the active cascode differential latch comprising;

a first input port;

a second input port;

a first transistor of a first conductivity type comprising a gate, and a drain connected to the first input port;

a second transistor of the first conductivity type comprising a gate, and a drain connected to the second input port;

a first active cascode transistor of the first conductivity type comprising a source connected to the drain of the first transistor, and a gate connected to the gate of the first transistor;

a second active cascode transistor of the first conductivity type comprising a source connected to the drain of the second transistor, and a gate connected to the gate of the second transistor; and

a load coupled to the first and second active cascode transistors.

14. The computer system as set forth in claim 13, wherein the load comprises:

a third transistor of a second conductivity type, the second conductivity type complementary to the first conductivity type, comprising a drain connected to the drain of the first active cascode transistor, and a gate connected to the gate of the first active cascode transistor and the drain of the second cascode transistor; and

a fourth transistor of a second conductivity type comprising a drain connected to the drain of the second active cascode transistor, and a gate connected to the gate of the second active cascode transistor and the drain of the first cascode transistor.

15. The computer system as set forth in claim 14, the active cascode differential latch further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.

16. The computer system as set forth in claim 13, the active cascode differential latch further comprising:

a pre-charge transistor to provide a low impedance path between the gates of the first and second transistors only if ON.