Level shifter

• US 20030222699A1
• Filed: 05/30/2002
• Published: 12/04/2003
• Est. Priority Date: 05/30/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Nowka, Kevin John, Carpenter, Gary Dale
• Granted Patent: US 6,717,452 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

A level shifter having a data input node, a first inverter having its input connected to the data input node, a second inverter connected to an output of the first inverter, a data output node, a latch having its output connected to the data output node, a first NFET connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter, and a second NFET connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter. The level shifter provides for a conversion of a data signal from a power supply domain of 1.8 volts to one of 3.3 volts.

Claims

1. A level shifter comprising:

a data input node;

a first inverter having its input connected to the data input node;

a second inverter connected to an output of the first inverter;

a data output node;

a latch having its output connected to the data output node;

a first NFET connected between an input of the latch and a ground potential, the first NFET having its gate electrode connected to an output of the second inverter; and

a second NFET connected between the data output node and the ground potential, the second NFET having its gate electrode connected to the output of the first inverter.

2. The level shifter as recited in claim 1, further comprising:

a first switching device connected between the output of the first inverter and the ground potential, wherein the first switching device receives a hold signal at its gate electrode.

3. The level shifter as recited in claim 1, further comprising:

a first switching device connected between the output of the second inverter and the ground potential, wherein the first switching device receives a hold signal at its gate electrode.

4. The level shifter as recited in claim 2, further comprising:

a second switching device connected between the output of the second inverter and the ground potential, wherein the second switching device receives the hold signal at its gate electrode.

5. The level shifter as recited in claim 1, further comprising:

a first switching device connected between the first inverter and a first power supply having a first potential, wherein the first switching device receives a hold signal at its gate electrode.

6. The level shifter as recited in claim 1, further comprising:

a first switching device connected between the second inverter and a first power supply having a first potential, wherein the first switching device receives a hold signal at its gate electrode.

7. The level shifter as recited in claim 6, further comprising:

a second switching device connected between the first inverter and the first power supply having the first potential, wherein the second switching device receives the hold signal at its gate electrode.

8. The level shifter as recited in claim 4, further comprising:

a third switching device connected between the first inverter and a first power supply having a first potential, wherein the third switching device receives the hold signal at its gate electrode; and

a fourth switching device connected between the second inverter and the first power supply having the first potential, wherein the fourth switching device receives the hold signal at its gate electrode.

9. The level shifter as recited in claim 1, wherein the first and second inverters are energized by a first power supply having a first potential, and wherein the latch is energized by a second power supply having a second potential.

10. The level shifter as recited in claim 9, wherein the first potential is 1.8 volts, and the second potential is 3.3 volts.

11. The level shifter as recited in claim 1, further comprising circuitry for isolating the first and second inverters from the latch.

12. A level shifter comprising:

first circuitry for receiving a data signal having a voltage swing from ground to 1.8 volts;

second circuitry for converting the data signal to have a voltage swing from ground to 3.3 volts; and

an output node for outputting the data signal with the voltage swing from ground to 3.3 volts.

13. The level shifter as recited in claim 12, further comprising:

circuitry for isolating the first circuitry from the second circuitry after the data signal has been converted to have the voltage swing from ground to 3.3 volts.

14. The level shifter as recited in claim 13, further comprising:

circuitry for disconnecting the first circuitry from a power supply providing the voltage swing from ground to 1.8 volts.

15. The level shifter as recited in claim 12, wherein the first circuitry comprises first and second NOR gates and wherein the second circuitry comprises a storage cell.

16. A data processing system comprising:

a microprocessor and accompanying circuitry outputting data signals with a voltage swing magnitude of 1.8 volts;

level shifter circuitry for converting the voltage swing magnitude of the data signals from 1.8 volts to 3.3 volts; and

input/output circuitry for receiving the data signals with the voltage swing magnitude of 3.3 volts.

17. The system as recited in claim 16, wherein the level shifter circuitry further comprises:

first circuitry for receiving the data signals having a voltage swing from ground to 1.8 volts; and

second circuitry for converting the data signals to have a voltage swing from ground to 3.3 volts.

18. The system as recited in claim 17, further comprising:

circuitry for isolating the first circuitry from the second circuitry after the data signals have been converted to have the voltage swing from ground to 3.3 volts.

19. The system as recited in claim 18, further comprising:

circuitry for disconnecting the first circuitry from a power supply providing the voltage swing from ground to 1.8 volts.

20. The system as recited in claim 16, wherein the level shifter circuitry further comprises:

a data input node for receiving the data signals;

a first inverter having its input connected to the data input node;

a second inverter connected to an output of the first inverter;

a data output node;

a latch having its output connected to the data output node;

a first switch connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter; and

a second switch connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter.

21. The system as recited in claim 20, further comprising circuitry for isolating the first and second inverters from the latch.

22. A level shifter comprising:

a data input node;

a first NOR gate coupled to the data input node;

a second NOR gate coupled to an output of the first NOR gate;

a storage cell coupled to an output of the second NOR gate; and

a data output node coupled to an output of the storage cell.

23. The level shifter as recited in claim 22, further comprising a first NFET coupled between the first NOR gate and the second NOR gate.

24. The level shifter as recited in claim 23, further comprising a second NFET coupled to the output of the first NOR gate and to the data output node.

25. The level shifter as recited in claim 22, wherein the first and second NOR gates are powered by a first voltage supply, and wherein the storage cell is powered by a second voltage supply, wherein the first and second voltage supplies have different voltages.

26. The level shifter as recited in claim 23, wherein the first and second NOR gates are configured to receive a hold signal.

27. The level shifter as recited in claim 22, wherein the first NOR gate receives a hold signal and a nonpersistent low voltage data signal, and generates a first NOR output signal, wherein the second NOR gate receiver the hold signal and the first NOR output signal, and generates a second NOR output signal, the level shifter further comprising circuitry for coupling the first NOR output signal and the second NOR output signal to complimentary inputs of the storage cell generating a persistent high voltage data signal.