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Multiplier-based processor-in-memory architectures for image and graphics processing

  • US 20030222879A1
  • Filed: 04/09/2003
  • Published: 12/04/2003
  • Est. Priority Date: 04/09/2002
  • Status: Active Grant
First Claim
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1. A computational random access memory comprising:

  • a memory comprising N columns, N being an integer; and

    an arithmetic logic unit, in communication with the N columns in the memory, the arithmetic logic unit comprising;

    M multipliers, m being an integer divisible into N, each of the m multipliers being configured to multiply two N/M-bit numbers; and

    an adder stage, in communication with the M multipliers to receive outputs of the M multipliers, for forming and outputting calculation results in accordance with the outputs of the M multipliers.

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